Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array

Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D...

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Bibliographic Details
Published in:Micromachines (Basel) 2021-05, Vol.12 (6), p.614
Main Authors: Chen, Zhisheng, Song, Renjun, Huo, Qiang, Ren, Qirui, Zhang, Chenrui, Li, Linan, Zhang, Feng
Format: Article
Language:English
Subjects:
3-D integration
Arrays
Circuits
Design
Electric potential
Impact analysis
Leakage current
Liability
Performance evaluation
Performance prediction
Power consumption
Random access memory
resistive random access memory (RRAM)
self-selective cell (SSC)
Simulation
sneak path
Voltage
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Summary:Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays.
ISSN:2072-666X
2072-666X
DOI:10.3390/mi12060614