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Hardware Implementation of Neuromorphic Computing Using Large‐Scale Memristor Crossbar Arrays
Brain‐inspired neuromorphic computing is a new paradigm that holds great potential to overcome the intrinsic energy and speed issues of traditional von Neumann based computing architecture. With the ability to perform vector‐matrix multiplications and flexible tunable conductance, the memristor cros...
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Published in: | Advanced intelligent systems 2021-01, Vol.3 (1), p.n/a |
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Main Authors: | , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | Brain‐inspired neuromorphic computing is a new paradigm that holds great potential to overcome the intrinsic energy and speed issues of traditional von Neumann based computing architecture. With the ability to perform vector‐matrix multiplications and flexible tunable conductance, the memristor crossbar array (CBA) structure is one of the most promising candidates to realize neural cognitive systems. The boom in the development of memristive synapses and neurons has propelled the developments of artificial neural networks (ANNs) to emulate the highly hierarchically organized network of human brain in the past decade. To achieve this, realizing large scale, high‐density memristive CBAs is a prerequisite to constructing complex ANNs. Herein, the stringent requirements in device performance and array parameters for hardware ANNs are analyzed, and the efforts in addressing the associated challenges are discussed. Recent progress on the experimental demonstration of neuromorphic computing systems (NCSs) is presented. Recommendations for further performance optimization at the device, circuit, and algorithm levels are proposed. This Report serves as a guide for the hardware implementation of NCS based on large‐scale CBAs.
The recent progress on hardware implementation of neuromorphic computing (NC) using large‐scale memristor crossbar arrays (MCBAs) is presented. The stringent requirements of memristor performance and array parameters along with the efforts in addressing the associated challenges are discussed. Recommendations for further performance optimization are proposed. This Report serves as a guide for hardware implementation of NC using MCBAs. |
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ISSN: | 2640-4567 2640-4567 |
DOI: | 10.1002/aisy.202000137 |