A novel nine‐level inverter, applicable in air plane ground power unit

• Published in: IET power electronics 2024-08, Vol.17 (11), p.1457-1467
• Main Authors: Ebrahimi, Reza, Kojabadi, Hossein Madadi
• Format: Article
• Language: English
• Subjects: DC‐AC power convertors; PWM invertors
• ISSN: 1755-4535; 1755-4543
• DOI: 10.1049/pel2.12712

In this study, a novel nine‐level inverter using one voltage source, 10 unidirectional and one bidirectional power switches, and two capacitors has been proposed to utilize in ground power units (GPUs). Selective harmonic elimination method has been applied to reduce the output voltage's THD to less than 3% with 115/200 V and 400 Hz. The proposed converter utilized a lower number of devices to output a nine‐level staircase in comparison to existing converters. Also, the proposed converter uses inherent self‐voltage balancing for capacitors' voltage. So, the control algorithm gets simpler. In this study, the topology analysis, modulation algorithm, capacitor calculation, loss, efficiency, and performance analysis of the proposed topology have been presented. The proposed circuit has been compared to recently published papers in terms of efficiency, switch, capacitor, diode, and source numbers. The theoretical and experimental performance of the topology has been verified by simulation on PSCAD and PSIM software and 350 W experimental setup. In this study, a novel nine‐level inverter using one voltage source, 10 unidirectional and one bidirectional power switches, and two capacitors has been proposed to utilize in ground power units (GPUs). Selective harmonic elimination method has been applied to reduce the output voltage's THD to less than 3% with 115/200 V and 400 Hz. The proposed converter utilized a lower number of devices to output a nine‐level staircase in comparison to existing converters. Also, the proposed converter uses inherent self‐voltage balancing for capacitors' voltage. So, the control algorithm gets simpler. In this study, the topology analysis, modulation algorithm, capacitor calculation, loss, efficiency, and performance analysis of the proposed topology have been presented. The proposed circuit has been compared to recently published papers in terms of efficiency, switch, capacitor, diode, and source numbers. The theoretical and experimental performance of the topology has been verified by simulation on PSCAD and PSIM software and 350W experimental setup.