Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal pr...

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Bibliographic Details
Published in:IET circuits, devices & systems devices & systems, 2021-08, Vol.15 (5), p.455-464
Main Authors: Tomar, Geetam Singh, George, Marcus Llyode, Tomar, Abhineet Singh
Format: Article
Language:English
Subjects:
Algorithms
Arithmetic and logic units
Design
Field programmable gate arrays
floating point arithmetic
Gate arrays
Image processing
logic design
Mathematical analysis
Mathematical functions
Mathematics
Multiplication
Multiplication & division
Multipliers
multiplying circuits
Semiconductor industry
Signal processing
Similarity
Simulation
Subtraction
Video
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Summary:Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as signal processing, video processing and image processing for which floating‐point multiplication is an important component. The dynamic range of numbers represented by floating‐point arithmetic is very large compared with that of fixed‐point numbers of the same bit width. A mantissa similarity investigator (MSI)–interfaced multi‐precision binary multiplier architecture is developed and can be used in data‐intensive applications that require variable precision, high throughput and low delay. This architecture can be configured to operate in single‐, double‐, quadruple‐ and octuple‐precision modes for mantissa multiplication according to the IEEE 754 standard for floating‐point numbers. The system produces increased throughput and utilises mantissa similarity to reduce system delay. The system was synthesised for a variety of field‐programmable gate array targets using Xilinx ISE Design Suite 14.7, and performance was simulated using that suite's ISim simulator.
ISSN:1751-858X
1751-8598
DOI:10.1049/cds2.12041