Enhancing the specific capacitance of a porous silicon-based capacitor by embedding graphene combined with three-dimensional electrochemical etching

• Published in: Electrochemistry communications 2023-09, Vol.154, p.107555, Article 107555
• Main Authors: Lin, Jia-Chuan, Liu, Yi-Cheng, Lu, Shan-Heng, Yen, Hsu-Nan, Settu, Kalpana
• Format: Article
• Language: English
• Subjects: Electrochemical etching; Laser trench; Porous silicon; Three-dimensional etching
• ISSN: 1388-2481; 1873-1902
• DOI: 10.1016/j.elecom.2023.107555

•First porous Si capacitor incorporating graphene and laser trenches.•Improved specific capacitance and equivalent permittivity of Si capacitor.•New innovation of 3-dimensional electrochemical etching of porous Si. A porous silicon-based capacitive structure with high specific capacitance is fabricated by three-dimensional electrochemical etching. As well as conventional planar electrochemical etching in two dimensions on the surface of a silicon chip, the lateral side walls of trenches engraved by a laser beam are also etched (third dimension). Platinum is deposited on both sides of the porous silicon film to create a capacitive structure that allows for stable measurement of the equivalent permittivity and specific capacitance of the trench-structured, layered porous silicon material. To eliminate the large parasitic effect due to the high roughness and air gaps between the metal layer and the porous silicon layer, nano-scale graphene is embedded into the surface pores of the porous silicon to enable good contact. After preliminary experiments, an etching approach based on a continuously decreasing current is adopted to obtain a strong porous silicon structure with long silicon pillars. Various laser engraving patterns were compared to determine the effect of three-dimensional etching. The results show that the increase in specific capacitance due to the laser trenches is positively correlated with the extent of lateral etching. The proposed method is suitable for improving the equivalent permittivity of the porous silicon layer without changing the device geometry or electrochemical etching parameters, and is also compatible with Si-VLSI technology.