Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates

In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthresh...

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Bibliographic Details
Published in:Journal of low power electronics and applications 2015-05, Vol.5 (2), p.116-129
Main Authors: Ogasahara, Yasuhiro, Nakagawa, Tadashi, Sekigawa, Toshihiro, Tsutsumi, Toshiyuki, Koike, Hanpei
Format: Article
Language:English
Subjects:
Chip formation
Chips
Electric potential
FD-SOI
Gates
Logic
measurement on silicon
Oxides
Silicon
SOTB
ultra-low voltage
Voltage
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Summary:In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips.
ISSN:2079-9268
2079-9268
DOI:10.3390/jlpea5020116