Memristive Structure-Based Chaotic System for PRNG

This paper suggests an approach to generate pseudo-random sequences based on the discrete-time model of the simple memristive chaotic system. We show that implementing Euler’s and Runge–Kutta’s methods for the simulation solutions gives the possibility of obtaining chaotic sequences that maintain ge...

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Bibliographic Details
Published in:Symmetry (Basel) 2022-01, Vol.14 (1), p.68
Main Authors: Haliuk, Serhii, Krulikovskyi, Oleh, Vovchuk, Dmytro, Corinto, Fernando
Format: Article
Language:English
Subjects:
Algorithms
balance property
Chaos theory
chaotic PRNG
Circuits
coupled chaotic systems
Digital signatures
Fixed point arithmetic
Generators
Mathematical models
memristive chaotic circuit
Noise
Pseudorandom sequences
Random numbers
Runge-Kutta method
Simulation
Statistical tests
symmetric encryption
Synchronism
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Summary:This paper suggests an approach to generate pseudo-random sequences based on the discrete-time model of the simple memristive chaotic system. We show that implementing Euler’s and Runge–Kutta’s methods for the simulation solutions gives the possibility of obtaining chaotic sequences that maintain general properties of the original chaotic system. A preliminary criterion based on the binary sequence balance estimation is proposed and applied to separate any binary representation of the chaotic time sequences into random and non-random parts. This gives us the possibility to delete obviously non-random sequences prior to the post-processing. The investigations were performed for arithmetic with both fixed and floating points. In both cases, the obtained sequences successfully passed the NIST SP 800-22 statistical tests. The utilization of the unidirectional asymmetric coupling of chaotic systems without full synchronization between them was suggested to increase the performance of the chaotic pseudo-random number generator (CPRNG) and avoid identical sequences on different outputs of the coupled systems. The proposed CPRNG was also implemented and tested on FPGA using Euler’s method and fixed-point arithmetic for possible usage in different applications. The FPGA implementation of CPRNG supports a generation speed up to 1.2 Gbits/s for a clock frequency of 50 MHz. In addition, we presented an example of the application of CPRNG to symmetric image encryption, but nevertheless, one is suitable for the encryption of any binary source.
ISSN:2073-8994
2073-8994
DOI:10.3390/sym14010068