A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

• Published in: Ingeniería e investigación 2007-09, Vol.27 (3), p.70-76
• Main Authors: Pacheco Bautista, Daniel, Castillo Soria, Francisco Rubén, Linares Aranda, Mónico, Salim Maza, Manuel
• Format: Article
• Language: English
• Subjects: clock recovery circuit; MCML logic; PLL; ring oscillator; VCO
• ISSN: 0120-5609; 2248-8723
• DOI: 10.15446/ing.investig.v27n3.14847

The clock recovery circuit (CRC) plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units) and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC) working at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL), current mode logic (MCML) and a novel two stage ring-based voltage controlled oscillator (VCO). The design used 0.35 µm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.