A novel read circuit for RRAM based on RC delay effect

In this paper, a novel Resistive Random‐Access Memory (RRAM) read circuit has been designed and verified by simulation based on the RRAM model and parasitic capacitance of the circuit. Simulation results demonstrate the feasibility and effectiveness of the proposed circuit, with accurate reading of...

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Bibliographic Details
Published in:Electronics letters 2023-10, Vol.59 (19), p.n/a
Main Authors: Ye, Jiabao, Cui, Xuecheng, Bi, Haoxiong, Cao, Jifang, Wang, Wannian, Xu, Xiaoxin, Liu, Dong, Chen, Bing
Format: Article
Language:English
Subjects:
Accuracy
Arrays
Effectiveness
memristors
Parasitics (electronics)
Performance evaluation
RC circuits
Reading
readout electronics
resistive RAM
Simulation
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Summary:In this paper, a novel Resistive Random‐Access Memory (RRAM) read circuit has been designed and verified by simulation based on the RRAM model and parasitic capacitance of the circuit. Simulation results demonstrate the feasibility and effectiveness of the proposed circuit, with accurate reading of RRAM states and fast reading speed in the nanosecond range. The sense margin of the proposed circuit has improved as the array size increases, enhancing its application for advanced node RRAM array manufacture. Compared with conventional circuits, the proposed circuit achieved power consumption reduction of 6% and area reduction of 46.9 um 2 , resulting in a 97.5% reduction in area, providing an effective solution to address the cost and chip size challenges associated with RRAM industrialization.
ISSN:0013-5194
1350-911X
DOI:10.1049/ell2.12964