Low complexity design of bit parallel polynomial basis systolic multiplier using irreducible polynomials

Encryption schemes like AES require finite field modular multiplication. The encryption speed is highly dependent on the performance of the finite field multiplier. Several high-speed systolic bit parallel multipliers with low area complexity have been proposed in the literature. In this paper, a mo...

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Bibliographic Details
Published in:Egyptian informatics journal 2022-03, Vol.23 (1), p.105-112
Main Authors: Devi, Sakshi, Mahajan, Rita, Bagai, Deepak
Format: Article
Language:English
Subjects:
Cryptography
Finite field
Nodes
Polynomial basis
Systolic architectures
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Summary:Encryption schemes like AES require finite field modular multiplication. The encryption speed is highly dependent on the performance of the finite field multiplier. Several high-speed systolic bit parallel multipliers with low area complexity have been proposed in the literature. In this paper, a modular multiplication algorithm is used to propose a bit parallel polynomial basis systolic multiplier which has achieved 89% less and 17% less area-delay product than the best existing multipliers. It has been observed that the area complexity of the proposed systolic multiplier for irreducible polynomials matches with the best-reported multiplier with 17% less time complexity. The results are further verified with the help of the FPGA implementation of the proposed multiplier for m = 8,163. Being generic, the proposed multiplier can be optimized further for trinomials and pentanomials.
ISSN:1110-8665
2090-4754
DOI:10.1016/j.eij.2021.07.003