Optimization of Processor Clock Frequency for Sensor Network Nodes Based on Energy Use and Timing Constraints

The effectiveness of sensor networks depends critically on efficient power management of the sensor nodes. Dynamic voltage frequency scaling (DVFS) and dynamic power management (DPM) have been proposed to enable energy-efficient scheduling for real-time and embedded systems. However, most power-awar...

Full description

Saved in:
Bibliographic Details
Published in:International journal of distributed sensor networks 2014-01, Vol.10 (6), p.617346
Main Authors: Kim, Youngmin, Joo, Heeju, Lee, Chan-Gun
Format: Article
Language:English
Subjects:
Algorithms
Analysis
Clocks
Dynamical systems
Dynamics
Energy efficiency
Energy use
Engineering research
Integrated circuits
Mathematical optimization
Methods
Microprocessors
Networks
Radio frequency
Scheduling (Management)
Sensors
Time measurements
Wireless networks
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The effectiveness of sensor networks depends critically on efficient power management of the sensor nodes. Dynamic voltage frequency scaling (DVFS) and dynamic power management (DPM) have been proposed to enable energy-efficient scheduling for real-time and embedded systems. However, most power-aware scheduling algorithms are designed to deal with only those cases in which the task execution time is determined solely by the clock frequency of the processor. In this study, we propose an extended task execution model that is appropriate for the sensor nodes and an algorithm that determines the optimal clock frequency for a node's processor. We analyze the extended model and verify that our algorithm calculates the clock frequency that optimizes energy savings while satisfying the timing constraints.
ISSN:1550-1477
1550-1329
1550-1477
DOI:10.1155/2014/617346