Joint security and performance improvement in multilevel shared caches

• Published in: IET information security 2021-07, Vol.15 (4), p.297-308
• Main Authors: Sarihi, Amin, Patooghy, Ahmad, Amininasab, Mahdi, Shokrolah Shirazi, Mohammad, A. Badawy, Abdel‐Hameed
• Format: Article
• Language: English
• Subjects: Algorithms; cache storage; Investment analysis; multiprocessing systems; resource allocation; Safety and security measures; Semiconductor industry
• ISSN: 1751-8709; 1751-8717
• DOI: 10.1049/ise2.12023

Multilevel cache architectures are widely used in modern heterogeneous systems for performance improvement. However, satisfying the performance and security requirements at the same time is a challenge for such systems. A simple and efficient timing attack on the shared portions of multilevel hierarchical caches and its corresponding countermeasure is proposed here. The proposed attack prolongs the execution time of the victim threads by inducing intentional race conditions in shared memory spaces. Then, a thread‐mapping algorithm to detect such race conditions between a group of threads and resolve them as a countermeasure against the attack is proposed. The proposed countermeasure dynamically monitors races on cache blocks and distributes existing and new threads on processing cores to minimize cache contention. Upon detection of a high contention rate that might be either due to an attack or a natural race condition, two mechanisms, namely cache access‐rate reduction and thread migration, will be used by the countermeasure algorithm to resolve the race situation. Evaluations on SPECCPU 2006 benchmark suite show that the proposed algorithm not only protects the system against the introduced attack but also boosts the overall system performance by an average of 46.35% and 55.92% for the worst and average cases, respectively.