Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress....

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Bibliographic Details
Published in:Memories - Materials, Devices, Circuits and Systems Devices, Circuits and Systems, 2023-07, Vol.4, p.100054, Article 100054
Main Authors: Sakui, Koji, Li, Yisuo, Kakumu, Masakazu, Kanazawa, Kenichi, Kunishima, Iwao, Iwata, Yoshihisa, Harada, Nozomu
Format: Article
Language:English
Subjects:
1T-DRAM
Capacitorless DRAM
FinFET
Floating Body
GAA
SOI
Surrounding Gate Transistor (SGT)
Z-RAM
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Summary:TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.
ISSN:2773-0646
2773-0646
DOI:10.1016/j.memori.2023.100054