Asynchronous SAR ADC with self‐timed track‐and‐hold

This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conver...

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Bibliographic Details
Published in:Electronics letters 2023-11, Vol.59 (22), p.n/a
Main Authors: Bae, Sunghyun, Lee, Sewon, Seong, Siheon, Woo, Jiwon, Lee, Minjae
Format: Article
Language:English
Subjects:
analogue‐digital conversion
Circuits
Conflicts of interest
mixed analogue‐digital integrated circuits
Time measurement
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Summary:This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases. This paper introduces a simple and effective Self‐Timed Track‐and‐Hold (STH) method that increases the timing margin for the conversion period without requiring a high‐speed input clock. When comparing the proposed STH method to the traditional Fixed‐Time Track‐and‐Hold (FTH) approach, the STH method consistently yields superior ENOB performance across a longer range of conversion periods.
ISSN:0013-5194
1350-911X
DOI:10.1049/ell2.13026