Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors

A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400-900 s). Subthreshold characteristics are improved and I off is drastically reduced (~two orders of magnitu...

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Bibliographic Details
Published in:IEEE journal of the Electron Devices Society 2019, Vol.7, p.959-963
Main Authors: Chung, Chris Chun-Chih, Ko, Chun-Ming, Chao, Tien-Sheng
Format: Article
Language:English
Subjects:
Chemicals
Degradation
fully silicided-S/D
Ions
junctionless
Logic gates
Low temperature
low-temperature trimming
monolithic 3D-ICs
Morphology
nanosheet
Nanosheets
poly-Si
Self-Limit
Silicidation
Silicides
Silicon
Surface morphology
Surface treatment
Transistors
Trimming
vertically stacked
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Summary:A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400-900 s). Subthreshold characteristics are improved and I off is drastically reduced (~two orders of magnitude) with increasing trimming cycles. Full silicidation on the source/drain (FUSI-S/D) is performed to improve I on . Surprisingly, after silicidation, both I on and μ FE shows degradation despite that the series resistance is improved. An ultrathin body junctionless (UTB-JL) device is fabricated to investigate the degradation cause by direct CV measurement on the device, which can give us an insight into the details of the change with the silicidation.
ISSN:2168-6734
2168-6734
DOI:10.1109/JEDS.2019.2940606