A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors

• Published in: Micromachines (Basel) 2023-05, Vol.14 (6), p.1107
• Main Authors: Yang, Jingwen, Huang, Ziqiang, Wang, Dawei, Liu, Tao, Sun, Xin, Qian, Lewen, Pan, Zhecheng, Xu, Saisheng, Wang, Chen, Wu, Chunlei, Xu, Min, Zhang, David Wei
• Format: Article
• Language: English
• Subjects: Circuit components; Dielectrics; Electric properties; Engineering; Epitaxy; Etching; Full BDI_Last; fully bottom dielectric isolation (BDI); Integrated circuits; Nanosheets; Oxidation; Power consumption; Power management; S/D-first; Semiconductor chips; Semiconductor industry; Si nanosheet gate-all-around (NS-GAA) transistors; TCAD simulation; Transistors
• ISSN: 2072-666X; 2072-666X
• DOI: 10.3390/mi14061107

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si Ge layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.