Architecture for Multiple Instruction Stream LSI Processors

Advancements of the semiconductor industry have produced an exponential increase in the capacity of integrated circuit chips. As this trend continues, much more complex systems will be able to be implemented on a single chip. This research is aimed at studying computer architectures which are most s...

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Bibliographic Details
Main Author: Kaminsky,William Joseph , Jr
Format: Report
Language:English
Subjects:
CIRCUIT INTERCONNECTIONS
COMPUTER ARCHITECTURE
Computer Hardware
Computer Systems
COST EFFECTIVENESS
Execution time
Independent processors
INTEGRATED CIRCUITS
Large scale integrated circuits
MICROPROCESSORS
MULTIPLEXING
Partitioning
Pin utilization
PINS
Pipelining
Solid State Physics
THESES
TIME SHARING
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Summary:Advancements of the semiconductor industry have produced an exponential increase in the capacity of integrated circuit chips. As this trend continues, much more complex systems will be able to be implemented on a single chip. This research is aimed at studying computer architectures which are most suited for LSI implementation. A pipelined multiprocessor architecture is derived and methodology given which determines a layout for such a processor from a given instruction set. The problem of partitioning a processor when it is too large for one chip is also examined. An evaluation of the performance of the pipelined processor as compared to a single stream processor is made. Three program traces are analyzed to study their usage of registers and this data is used to determine the performance of the processors with various degrees of pipelining and number of data registers. (Author) Doctoral thesis.