A Coherent VLSI Design Environment

The CAD frame Schema has been outfitted with a uniform protocol or aggregate data structures, which includes new control structures for examining and searching through the data structures. Circuit simulators installed in Schema can now use their own scratchpad, and call a variety of tools to deal wi...

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Bibliographic Details
Main Authors: Penfield, Paul, Jr, Dally, William J, Glasser, Lance A, Knight, Thomas F , Jr, Leiserson, Charles E
Format: Report
Language:English
Subjects:
CIRCUIT ANALYSIS
CIRCUITS
COMPUTER AIDED DESIGN
DATA BASES
Electrical and Electronic Equipment
GATES(CIRCUITS)
INTEGRATED CIRCUITS
METAL OXIDE SEMICONDUCTORS
Mfg & Industrial Eng & Control of Product Sys
NUMERICAL ANALYSIS
POWER
Protocols
REACTIVITIES
ROUTING
SIGNALS
SIMULATORS
STRUCTURES
TRANSIENTS
VLSI(Very Large Scale Integration)
WAVEFORMS
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Description
Summary:The CAD frame Schema has been outfitted with a uniform protocol or aggregate data structures, which includes new control structures for examining and searching through the data structures. Circuit simulators installed in Schema can now use their own scratchpad, and call a variety of tools to deal with the pertinent data structures. Waveform bounding results are now beginning to be available for ECL circuits, similar to those reported earlier for MOS interconnect and gates. The principal problem is that a vastly different gate model appears to be necessary for rising and falling transients. So far results within a few percent of SPICE have been obtained for some cases. A new procedure for calculating maximum frequency response of networks made from classes of devices with certain types of small-signal models, connected in arbitrary ways that conserve real and reactive power, has been worked out. This activity required the development of a new procedure to test whether 0 is in the numerical range of a non-Hermitian matrix.