A 4-Kbit Four-Transistor Dynamic Ram

The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of 160ns and power dissipation...

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Bibliographic Details
Main Author: Walker, Hank
Format: Report
Language:English
Subjects:
ACCESS TIME
CELLS
Computer Hardware
DISSIPATION
ENERGY CONSERVATION
POWER
RANDOM ACCESS COMPUTER STORAGE
TRANSISTORS
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Description
Summary:The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of 160ns and power dissipation of 160nW.