Utilizing Hardware Features for Secure Thread Management

• Main Author: Isa, Haruna R
• Format: Report
• Language: English
• Subjects: C4I(COMAND CONTROL COMMUNICATIONS COMPUTERS AND INTELLIGENCE); COMMAND CONTROL COMMUNICATIONS; Command, Control and Communications Systems; COMPUTER ARCHITECTURE; Computer Systems Management and Standards; COMPUTERS; COSTS; DATA PROCESSING SECURITY; DEPARTMENT OF DEFENSE; ENVIRONMENTS; ISOLATION; MANAGEMENT INFORMATION SYSTEMS; NAVY; POLICIES; PROCESSING; QUEUEING THEORY; SCHEDULING; SECURITY; SWITCHING; TCB(TRUSTED COMPUTING BASE)

Transaction processing (TP) applications are of use when solving a wide variety of data processing problems. Current commercial TP systems do not possess the ability to manage information at multiple security levels with high assurance. Department of Defense and Department of Navy Command, Control, Communication, Computers and Intelligence (C4I) applications handle information over a wide variety of classifications and compartments. The existence of TP applications that can securely process information of different classifications (with assurance) would save the DoD the need to create separate single level systems to process all necessary information. A trusted computing base (TCB) and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment has been designed. Intel's Pentium CPU architecture provides hardware with two distinct descriptor tables. One is used in the usual way for process isolation while the other is used for thread isolation. This allocation, together with an appropriately designed scheduling policy, permits us to avoid the full cost of process creation when only switching between threads of different security classes in the same process. where large numbers of transactions are encountered on transaction queues, this approach has benefits over traditional multilevel systems. Master's thesis.