Architectures for Cognitive Systems

• Main Author: Renz, Thomas E
• Format: Report
• Language: English
• Subjects: CHIPS(ELECTRONICS); CLUSTERING; COGNITION; COGNITIVE OPERATIONS; COMPUTER ARCHITECTURE; Computer Hardware; COMPUTERS; EFFICIENCY; HUMAN SDCALE COMPUTING; INTEGRATION; MODULAR CONSTRUCTION; NODES; OPTIMIZATION; PARALLEL ORIENTATION; PARALLEL PROCESSING; PE61102F; POWER; PROCESSING EQUIPMENT; SYSTEMS ANALYSIS; WUAFRL459TACPM

The Architectures for Cognitive Systems research project developed a computer core that is optimized to perform massively parallel cognitive computing operations such as are required for performance of cognitive primitive operations. A highly modular many node chip was designed which addressed power efficiency to the maximum extent possible. Each node contains an Asynchronous Field Programmable Gate Array, AFPGA, on board Static Random Access Memory, SRAM, and an Application Specific Processor core, ASP. The ultimate aim of this architecture was the creation of a dynamically configurable, highly parallel cluster of many modular nodes, to provide power efficient hardware optimization to perform complex cognitive computing operations. This project focused on the design of the core and integration across a four node chip. A follow on project will focus on creating a 3 dimensional stack of chips that is enabled by the low power usage. The chip incorporates structures to enable stacking in a small form factor. A third project will focus on system architecture issues, using many stacks to create a neuromorphic computing platform. This report describes the completed design trades and architecture for the nodes and chip level integration. At the end of the project, the chip design was nearly ready for fabrication and will be fabricated in the first part of a follow on project. The original document contains color images.