40 GSps, 6-bit RF DAC Design Report

This report details the design of a 40 GSps, 6-bit radio frequency (RF) digital-to-analog converter (DAC). The technology used is IBM 45 nm complementary metal oxide (CMOS) silicon-on-insulator (SOI). The architecture of the DAC is a novel approach of interleaving multiple subDACs in such a way that...

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Bibliographic Details
Main Author: Wilson, James E
Format: Report
Language:English
Subjects:
BROADBAND
COMPLEMENTARY METAL OXIDE SEMICONDUCTORS
Computer Hardware
DIGITAL TO ANALOG CONVERTERS
RADIOFREQUENCY
Radiofrequency Wave Propagation
SILICON ON INSULATOR
TRANSMITTERS
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Summary:This report details the design of a 40 GSps, 6-bit radio frequency (RF) digital-to-analog converter (DAC). The technology used is IBM 45 nm complementary metal oxide (CMOS) silicon-on-insulator (SOI). The architecture of the DAC is a novel approach of interleaving multiple subDACs in such a way that the nyquist images cancel each other out, allowing beyond Nyquist use of the subDACs. This technique is leveraged to build the 40 GSps speed using 10 GSps subDACs, allowing instantaneous bandwidth of 20 GHz. The original document contains color images.