3D structures for silicon carbide transistors utilising Al2O3 as a gate dielectric

• Published in: Materials science in semiconductor processing 2021-06, Vol.128, Article 105727
• Main Authors: Idris, M. Idzdihar, Horsfall, Alton B.
• Format: Article
• Language: English
• Subjects: 3-dimensional; 4H-SiC; Interface state density; Nanoscale transistor; Oxide capacitance
• ISSN: 1369-8001; 1873-4081
• DOI: 10.1016/j.mssp.2021.105727

This paper reports on the first investigation of the characteristics of 3D structures formed in silicon carbide for the realisation of ultra-high performance nanoscale transistors, based on the FINFET topology. Capacitance–voltage characteristics show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices. Two distinct peaks in the conductance–voltage characteristics are observed, centred at the flatband voltages, where the amplitude of the high voltage peak correlates with the sidewall area. This suggests that the chemical behaviour of the sidewalls differ from those of the (0001) wafer surface. The breakdown electric field of the dielectric film grown on the 3D structure is in excess of 3 MV cm−1. It is demonstrated that 3D transistors (FINFETs) do not utilise the gate voltage range where the abnormal characteristics exist and so this work reports for the first time the possibility of high performance nanoscale transistors in silicon carbide that can operate at high temperatures. [Display omitted] •The characteristics of 3D structures formed in silicon carbide is investigated.•C–V characteristics show evidence of a second flatband voltage.•Two distinct peaks in the conductance–voltage characteristics are observed.•The peak located at high bias correlates with the behaviour of the sidewall area.