An area efficient 64 point Radix-42 MDC FFT architecture for OFDM applications

• Published in: Integration (Amsterdam) 2024-11, Vol.99, Article 102244
• Main Authors: Rao, M. Srinivasa, Madhumati, G.L., Sailaja, M.
• Format: Article
• Language: English
• Subjects: Constant multiplier; MDC; Radix-42
• ISSN: 0167-9260
• DOI: 10.1016/j.vlsi.2024.102244

In this research,we present a 64-point radix-42 pipelined Fast Fourier Transform(FFT) architecture which is area-efficient for an orthogonal frequency division multiplexing(OFDM) based IEEE 802.11a wireless Local area network(LAN) baseband. We adopt Multiple Delay Commutator(MDC) architecture for hardware implementation. The proposed 64-point FFT adopts a modified constant multiplier to compute complex multiplication in place of complex multipliers and to avoid read-only memory(ROM),which is used to store twiddle factor coefficients internally. The area of the design is reduced by using modified constant multiplier. The proposed radix-42 pipelined FFT architecture is synthesized using 45 nm CMOS technology with a supply voltage of 1.1 V. The proposed design occupies 15.31K total gates,dissipates 8.6 mW of power and the power delay product is 430e−12. •A 64-point radix-42 pipelined FFT MDC architecture which is area efficient for OFDM applications.•The complex multipliers are replaced by constant multipliers with less area.•No need of memory to store the twiddle-factors.•The area of the processor is less compared with previous approaches.