The Effect of Diluted N[sub.2]O Annealing Time on Gate Dielectric Reliability of SiC Metal-Oxide Semiconductor Capacitors and Characterization of Performance on SiC Metal-Oxide Semiconductor Field Effect Transistor

• Published in: Electronics (Basel) 2024-01, Vol.13 (3)
• Main Authors: Dong, Zhihua, Jiang, Leifeng, Su, Manqi, Zeng, Chunhong, Liu, Hui, Li, Botong, Sun, Yuhua, Cui, Qi, Zeng, Zhongming, Zhang, Baoshun
• Format: Article
• Language: English
• Subjects: Capacitors; Design and construction; Integrated circuit fabrication; Metal oxide semiconductor field effect transistors; Methods; Silicon carbide
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics13030596

We performed dry oxidation on n-type silicon carbide (SiC), followed by annealing in diluted N[sub.2] O, and subsequently fabricated n-type MOS structures. The study aimed to investigate the impact of different annealing times on the trap charges near the SiC/SiO[sub.2] interface and the reliability of the gate dielectric. Capacitance-voltage (C-V) and current-voltage (I-V) measurements of the n-type MOS revealed that increasing the annealing time with N[sub.2] O effectively reduces the density of electron traps near the SiC/SiO[sub.2] interface, mitigates the drift in flat-band voltage and enhances the oxide breakdown field strength. However, excessive annealing time leads to an increase in the flat-band voltage drift of the MOS, resulting in premature oxide breakdown. Using the optimized annealing conditions, we fabricated n-type LDMOSFETs and obtained the threshold voltage (Vth), field-effect mobility (μ[sub.FE] ) and specific on-resistance (Ron-sp) from the transfer curve (Id-Vg) and output curve (Id-Vd) measurements. The research findings provide valuable insights for the gate oxidation process of SiC.