Area and power efficient frequency divider for Zigbee frequency synthesizer

This paper proposes an area and power efficient frequency divider used infrequency synthesisers, which operates in 2.4 GHz IEEE 802.15.4/ZigBee frequency band. The proposed frequency divider consists of a multi-modulus pre-scaler and integrated P&S counter. In order to reduce the power consumpti...

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Bibliographic Details
Published in:Australian journal of electrical & electronics engineering 2014-02, Vol.11 (1), p.7
Main Authors: Sundhari, R.P. Meenaakshi, Jagadeeshwaran, C, Nandhakumar, R
Format: Article
Language:English
Subjects:
Circuit design
Complementary metal oxide semiconductors
Energy use
Online Access:Get full text
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Summary:This paper proposes an area and power efficient frequency divider used infrequency synthesisers, which operates in 2.4 GHz IEEE 802.15.4/ZigBee frequency band. The proposed frequency divider consists of a multi-modulus pre-scaler and integrated P&S counter. In order to reduce the power consumption and area, swallow counter has been replaced by a simple digital circuit. Simulation results show 30% of area and power is reduced when compared to the previous design. All of the circuits can be designed in 0.18 µm complementary metal oxide semiconductor technology with a single 1.8 V DC voltage supply. KEYWORDS: DFF; frequency synthesiser; U-TSPC; PLL; true single-phase clock (TSPC).
ISSN:1448-837X
DOI:10.7158/E13-038.2014.11.1.