Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection

•A strategy to design BBICS with optimal fault detection sensitivity is proposed.•An asymmetry in the flipping ability of the sensor’s latch is introduced.•Low and high threshold voltage transistors are used to increase sensitivity.•No redesign of the standard cells in CMOS 65-nm is required. Bulk B...

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Bibliographic Details
Published in:Microelectronics and reliability 2013-09, Vol.53 (9-11), p.1320-1324
Main Authors: Dutertre, J.M., Possamai Bastos, R., Potin, O., Flottes, M.L., Rouzeyre, B., Di Natale, G.
Format: Article
Language:English
Subjects:
Applied sciences
Asymmetry
CMOS
Delay
Design. Technologies. Operation analysis. Testing
Electronics
Engineering Sciences
Exact sciences and technology
General equipment and techniques
Instruments, apparatus, components and techniques common to several branches of physics and astronomy
Integrated circuits
Micro and nanotechnologies
Microelectronics
Optimization
Physics
Power consumption
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sensors
Sensors (chemical, optical, electrical, movement, gas, etc.)
remote sensing
Strategy
Testing, measurement, noise and reliability
Transistors
Tuning
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Summary:•A strategy to design BBICS with optimal fault detection sensitivity is proposed.•An asymmetry in the flipping ability of the sensor’s latch is introduced.•Low and high threshold voltage transistors are used to increase sensitivity.•No redesign of the standard cells in CMOS 65-nm is required. Bulk Built-In Current Sensors (BBICSs) are able to detect anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. This paper presents a new strategy to design BBICSs with optimal transient-fault detection sensitivity while keeping low both area and power overheads. The approach allows increasing the detection sensitivity by setting an asymmetry in the flipping ability of the sensor’s latch. In addition, we introduce a mechanism to tune the delay of the bulk access transistors that improves even more the BBICS detection sensitivity. The proposed design strategy offers a good compromise between fault detection sensitivity and power consumption; moreover it makes feasible the use of several CMOS processes.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2013.07.069