Floating-Point Exponentiation Units for Reconfigurable Computing

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function x y as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and...

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Published in:ACM transactions on reconfigurable technology and systems 2013-05, Vol.6 (1), p.1-15
Main Authors: de Dinechin, Florent, Echeverría, Pedro, López-Vallejo, Marisa, Pasca, Bogdan
Format: Article
Language:English
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Computer Arithmetic
Computer Science
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description The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function x y as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.
doi_str_mv 10.1145/2457443.2457447
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source Association for Computing Machinery:Jisc Collections:ACM OPEN Journals 2023-2025 (reading list)
subjects Computer Arithmetic
Computer Science
title Floating-Point Exponentiation Units for Reconfigurable Computing
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