Degradation of n-channel a-Si:H/nc-Si:H bilayer thin-film transistors under DC electrical stress

• Published in: Microelectronics and reliability 2008-04, Vol.48 (4), p.531-536
• Main Authors: Arpatzanis, N., Hatzopoulos, A.T., Tassis, D.H., Dimitriadis, C.A., Templier, F., Oudwan, M., Kamarinos, G.
• Format: Article
• Language: English
• Subjects: Applied sciences; Condensed Matter; Electronics; Exact sciences and technology; Microelectronic fabrication (materials and surfaces technology); Other; Physics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2007.11.003

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress ( V G = 25 V, V D = 0), (ii) on-state bias stress ( V G = 25 V, V D = 20 V) and (iii) off-state bias stress ( V G = −25 V, V D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.