Analog/RF Performance of Multichannel SOI MOSFET

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, all...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2009-07, Vol.56 (7), p.1473-1482
Main Authors: Tao Chuan Lim, Bernard, E., Rozeau, O., Ernst, T., Guillaumot, B., Vulliet, N., Buj-Dufournet, C., Paccaud, M., Lepilliet, S., Dambrine, G., Danneville, F.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
Data mining
Devices
Early voltage
Electronics
Exact sciences and technology
FinFETs
Gates
Hafnium
Hafnium oxide
high frequency (HF)
Logic gates
MOSFETs
Multichannel
multichannel MOSFET
Radio frequencies
Radio frequency
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
Silicon
silicon-on-insulator (SOI)
Simulation
Spacers
Transistors
voltage gain
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Summary:In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance ( gm ) and very low output conductance, the RF/analog performances of MCFET-voltage gain ( A VI ) and early voltage ( V EA ) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency ( fT ), due to the large total input gate capacitances ( C GG ). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT . The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2009.2021438