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Analog/RF Performance of Multichannel SOI MOSFET
In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, all...
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Published in: | IEEE transactions on electron devices 2009-07, Vol.56 (7), p.1473-1482 |
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container_title | IEEE transactions on electron devices |
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creator | Tao Chuan Lim Bernard, E. Rozeau, O. Ernst, T. Guillaumot, B. Vulliet, N. Buj-Dufournet, C. Paccaud, M. Lepilliet, S. Dambrine, G. Danneville, F. |
description | In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance ( gm ) and very low output conductance, the RF/analog performances of MCFET-voltage gain ( A VI ) and early voltage ( V EA ) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency ( fT ), due to the large total input gate capacitances ( C GG ). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT . The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications. |
doi_str_mv | 10.1109/TED.2009.2021438 |
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Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance ( gm ) and very low output conductance, the RF/analog performances of MCFET-voltage gain ( A VI ) and early voltage ( V EA ) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency ( fT ), due to the large total input gate capacitances ( C GG ). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT . The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2009.2021438</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Capacitance ; Data mining ; Devices ; Early voltage ; Electronics ; Exact sciences and technology ; FinFETs ; Gates ; Hafnium ; Hafnium oxide ; high frequency (HF) ; Logic gates ; MOSFETs ; Multichannel ; multichannel MOSFET ; Radio frequencies ; Radio frequency ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Semiconductors ; Silicon ; silicon-on-insulator (SOI) ; Simulation ; Spacers ; Transistors ; voltage gain</subject><ispartof>IEEE transactions on electron devices, 2009-07, Vol.56 (7), p.1473-1482</ispartof><rights>2009 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c417t-388287a794b3cfffbc8a76497c970aa9d473a93e0792114feefeb5fbce7772f83</citedby><cites>FETCH-LOGICAL-c417t-388287a794b3cfffbc8a76497c970aa9d473a93e0792114feefeb5fbce7772f83</cites><orcidid>0000-0002-4725-0010</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5061648$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,314,780,784,885,27924,27925,54796</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=21884676$$DView record in Pascal Francis$$Hfree_for_read</backlink><backlink>$$Uhttps://hal.science/hal-00469684$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Tao Chuan Lim</creatorcontrib><creatorcontrib>Bernard, E.</creatorcontrib><creatorcontrib>Rozeau, O.</creatorcontrib><creatorcontrib>Ernst, T.</creatorcontrib><creatorcontrib>Guillaumot, B.</creatorcontrib><creatorcontrib>Vulliet, N.</creatorcontrib><creatorcontrib>Buj-Dufournet, C.</creatorcontrib><creatorcontrib>Paccaud, M.</creatorcontrib><creatorcontrib>Lepilliet, S.</creatorcontrib><creatorcontrib>Dambrine, G.</creatorcontrib><creatorcontrib>Danneville, F.</creatorcontrib><title>Analog/RF Performance of Multichannel SOI MOSFET</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance ( gm ) and very low output conductance, the RF/analog performances of MCFET-voltage gain ( A VI ) and early voltage ( V EA ) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency ( fT ), due to the large total input gate capacitances ( C GG ). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT . The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.</description><subject>Applied sciences</subject><subject>Capacitance</subject><subject>Data mining</subject><subject>Devices</subject><subject>Early voltage</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>FinFETs</subject><subject>Gates</subject><subject>Hafnium</subject><subject>Hafnium oxide</subject><subject>high frequency (HF)</subject><subject>Logic gates</subject><subject>MOSFETs</subject><subject>Multichannel</subject><subject>multichannel MOSFET</subject><subject>Radio frequencies</subject><subject>Radio frequency</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Semiconductors</subject><subject>Silicon</subject><subject>silicon-on-insulator (SOI)</subject><subject>Simulation</subject><subject>Spacers</subject><subject>Transistors</subject><subject>voltage gain</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><recordid>eNp9kc1LwzAYh4MoOKd3wUsRVDx0S5o0H8cxNzfYmLh5DllMXEfWarIK_vemdOzgwUtC3jzvj-R9ALhGsIcQFP3V6KmXQSjikiGC-QnooDxnqaCEnoIOhIinAnN8Di5C2MYjJSTrADgolas--q_j5MV4W_mdKrVJKpvMa7cv9EaVpXHJcjFN5ovleLS6BGdWuWCuDnsXvMXqcJLOFs_T4WCWaoLYPsWcZ5wpJsgaa2vtWnPFKBFMCwaVEu-EYSWwgUxkCBFrjDXrPGKGMZZZjrvgsc3dKCc_fbFT_kdWqpCTwUw2NQgJFZSTbxTZh5b99NVXbcJe7oqgjXOqNFUdJKeCE0ayJvX-XxJTjAmGIoK3f8BtVfs4q5iWUxH_BmmEYAtpX4XgjT0-FEHZWJHRimysyIOV2HJ3yFVBK2d9HHcRjn0Z4pxQ1kTftFxhjDle55BGbxz_ApVGkQo</recordid><startdate>20090701</startdate><enddate>20090701</enddate><creator>Tao Chuan Lim</creator><creator>Bernard, E.</creator><creator>Rozeau, O.</creator><creator>Ernst, T.</creator><creator>Guillaumot, B.</creator><creator>Vulliet, N.</creator><creator>Buj-Dufournet, C.</creator><creator>Paccaud, M.</creator><creator>Lepilliet, S.</creator><creator>Dambrine, G.</creator><creator>Danneville, F.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Semiconductors</topic><topic>Silicon</topic><topic>silicon-on-insulator (SOI)</topic><topic>Simulation</topic><topic>Spacers</topic><topic>Transistors</topic><topic>voltage gain</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tao Chuan Lim</creatorcontrib><creatorcontrib>Bernard, E.</creatorcontrib><creatorcontrib>Rozeau, O.</creatorcontrib><creatorcontrib>Ernst, T.</creatorcontrib><creatorcontrib>Guillaumot, B.</creatorcontrib><creatorcontrib>Vulliet, N.</creatorcontrib><creatorcontrib>Buj-Dufournet, C.</creatorcontrib><creatorcontrib>Paccaud, M.</creatorcontrib><creatorcontrib>Lepilliet, S.</creatorcontrib><creatorcontrib>Dambrine, G.</creatorcontrib><creatorcontrib>Danneville, F.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Hyper Article en Ligne (HAL)</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tao Chuan Lim</au><au>Bernard, E.</au><au>Rozeau, O.</au><au>Ernst, T.</au><au>Guillaumot, B.</au><au>Vulliet, N.</au><au>Buj-Dufournet, C.</au><au>Paccaud, M.</au><au>Lepilliet, S.</au><au>Dambrine, G.</au><au>Danneville, F.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analog/RF Performance of Multichannel SOI MOSFET</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2009-07-01</date><risdate>2009</risdate><volume>56</volume><issue>7</issue><spage>1473</spage><epage>1482</epage><pages>1473-1482</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO 2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned silicon bodies (UTBs). In other words, the operation of the MCFET is theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET with a gate length of 50 nm are extracted and discussed. Thanks to the enormous transconductance ( gm ) and very low output conductance, the RF/analog performances of MCFET-voltage gain ( A VI ) and early voltage ( V EA ) are superior compared with that of the single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency ( fT ), due to the large total input gate capacitances ( C GG ). This inspires the introduction of spacer engineering in MCFET, aiming at improving both C GG and fT . The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2009.2021438</doi><tpages>10</tpages><orcidid>https://orcid.org/0000-0002-4725-0010</orcidid></addata></record> |
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subjects | Applied sciences Capacitance Data mining Devices Early voltage Electronics Exact sciences and technology FinFETs Gates Hafnium Hafnium oxide high frequency (HF) Logic gates MOSFETs Multichannel multichannel MOSFET Radio frequencies Radio frequency Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors Silicon silicon-on-insulator (SOI) Simulation Spacers Transistors voltage gain |
title | Analog/RF Performance of Multichannel SOI MOSFET |
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