Design challenges of a fully integrated 65 nm CMOS half cascode SFDS PA

This paper presents the measurement results of a wideband multi-standards fully integrated 65 nm CMOS-power amplifier (PA). This PA is based on a half stacked folded pseudo-differential structure (HSFDS) cascoded. This demonstrator is composed by only one stage. It provides a maximal gain of 10 dB a...

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Bibliographic Details
Published in:Analog integrated circuits and signal processing 2012-02, Vol.70 (2), p.181-187
Main Authors: Luque, Y., Kerhervé, E., Deltimple, N., Belot, D.
Format: Article
Language:English
Subjects:
Circuits and Systems
Electrical Engineering
Engineering
Engineering Sciences
Micro and nanotechnologies
Microelectronics
Signal,Image and Speech Processing
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Summary:This paper presents the measurement results of a wideband multi-standards fully integrated 65 nm CMOS-power amplifier (PA). This PA is based on a half stacked folded pseudo-differential structure (HSFDS) cascoded. This demonstrator is composed by only one stage. It provides a maximal gain of 10 dB at 2.2 GHz with a bandwidth at −3 dB ( B w - 3   dB ) of 43%. At 1.95 GHz, the maximal output power ( P max ) is 23.3 dBm with a power added efficiency (PAE) of 12%. The output power at 1 dB compression ( OCP 1 ) is 21 dBm. At 2.4 GHz, Pmax is 23 dBm with a PAE of 11.3%. At this frequency, the OCP1 is 20 dBm.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-011-9735-1