Electrical compact modelling of graphene transistors

• Published in: Solid-state electronics 2012-07, Vol.73, p.27-31
• Main Authors: Frégonèse, Sébastien, Meng, Nan, Nguyen, Huu-Nha, Majek, Cedric, Maneux, Cristell, Happy, Henri, Zimmer, Thomas
• Format: Article
• Language: English
• Subjects: Amplifiers; Applied sciences; Circuit; Circuit design; Circuit properties; Compact; Devices; Electric, optical and optoelectronic circuits; Electrical; Electronic circuits; Electronics; Exact sciences and technology; Graphene; LNA; Miscellaneous; Noise; Noise levels; Power gain; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SPICE; Transistor; Transistors
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2012.02.002

► A compact model for graphene FET device. ► Traps effects have been taken into account. ► Model has been compared to measurement in DC and AC regime. ► A LNA has been designed. An electrical compact model for graphene FET device is proposed. Starting from Meric’s compact model, a trap model is introduced and the equivalent circuit is improved. We show that traps have an effect on the transconductance and influence consequently most figures of merit in circuit design. The model has been verified by comparison to DC and AC measurements versus bias and frequency on an advanced GFET having a transit frequency of about 10GHz. Then, the compact model has been used to evaluate the transistor in a circuit context. A LNA has been designed and despite the poor voltage gain of the GFET, the LNA shows interesting performances when input and output matching of the circuit is performed. A power gain of |S21|=4.2dB is obtained, the reverse isolation is about |S12|=−10.6dB, the Rollet stability factor K is 1.25 and the noise figure is 3.9dB at 800MHz.