OCEAN, a flexible adaptive Network-On-Chip for dynamic applications

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure...

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Bibliographic Details
Published in:Microprocessors and microsystems 2014-06, Vol.38 (4), p.337-357
Main Authors: Devaux, Ludovic, Pillement, Sebastien
Format: Article
Language:English
Subjects:
ASIC
Dynamic and partial reconfiguration
Dynamic tests
Dynamics
Engineering Sciences
Field programmable gate arrays
FPGA
Interconnection
Network On Chip
Networks
OCEAN
Oceans
Reconfiguration
Tasks
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Description
Summary:The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2014.02.002