A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

• Published in: IEEE journal of solid-state circuits 2017-01, Vol.52 (1), p.33-49
• Main Authors: Vivet, Pascal, Thonnart, Yvain, Lemaire, Romain, Santos, Cristiano, Beigné, Edith, Bernard, Christian, Darve, Florian, Lattard, Didier, Miro-Panades, Ivan, Dutoit, Denis, Clermidy, Fabien, Chéramy, Séverine, Sheibanyrad, Abbas, Pétrot, Frédéric, Flamand, Eric, Michailos, Jean, Arriordaz, Alexandre, Wang, Lee, Schloeffel, Juergen
• Format: Article
• Language: English
• Subjects: Computer Science; Engineering Sciences
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2016.2611497

Future many cores, either for high performance computing or for embedded applications, are facing the powerwall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through siliconvia (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipationdevoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, interms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eightdie layers.