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An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory
Summary A parallel program needs to manage the trade‐off between the time spent in synchronisation and computation. This trade‐off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread pla...
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Published in: | Concurrency and computation 2018-09, Vol.30 (18), p.n/a |
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container_title | Concurrency and computation |
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creator | Zhou, Naweiluo Delaval, Gwenaël Robu, Bogdan Rutten, Éric Méhaut, Jean‐François |
description | Summary
A parallel program needs to manage the trade‐off between the time spent in synchronisation and computation. This trade‐off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well‐mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time. |
doi_str_mv | 10.1002/cpe.4506 |
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A parallel program needs to manage the trade‐off between the time spent in synchronisation and computation. This trade‐off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well‐mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time.</description><identifier>ISSN: 1532-0626</identifier><identifier>EISSN: 1532-0634</identifier><identifier>DOI: 10.1002/cpe.4506</identifier><language>eng</language><publisher>Hoboken: Wiley Subscription Services, Inc</publisher><subject>Access time ; autonomic computing ; Computer architecture ; Computer memory ; Computer Science ; Computing costs ; Computing time ; Concurrency ; Concurrent processing ; Control systems ; Distributed, Parallel, and Cluster Computing ; Dynamic control ; Feedback control ; Locks ; Mapping ; Microprocessors ; Parallel programming ; parallelism ; synchronisation ; thread mapping ; Time synchronization ; transactional memory</subject><ispartof>Concurrency and computation, 2018-09, Vol.30 (18), p.n/a</ispartof><rights>Copyright © 2018 John Wiley & Sons, Ltd.</rights><rights>2018 John Wiley & Sons, Ltd.</rights><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c3276-c512e73501b9e58f23502aed812c3f4e3d565bb1ff77efd20a932ce48140e5443</citedby><cites>FETCH-LOGICAL-c3276-c512e73501b9e58f23502aed812c3f4e3d565bb1ff77efd20a932ce48140e5443</cites><orcidid>0000-0001-9329-4500 ; 0000-0003-1047-7462 ; 0009-0000-3029-7384 ; 0000-0001-8696-8212 ; 0000-0001-7568-007X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>230,314,777,781,882,27905,27906</link.rule.ids><backlink>$$Uhttps://hal.science/hal-01742690$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Zhou, Naweiluo</creatorcontrib><creatorcontrib>Delaval, Gwenaël</creatorcontrib><creatorcontrib>Robu, Bogdan</creatorcontrib><creatorcontrib>Rutten, Éric</creatorcontrib><creatorcontrib>Méhaut, Jean‐François</creatorcontrib><title>An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory</title><title>Concurrency and computation</title><description>Summary
A parallel program needs to manage the trade‐off between the time spent in synchronisation and computation. This trade‐off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well‐mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time.</description><subject>Access time</subject><subject>autonomic computing</subject><subject>Computer architecture</subject><subject>Computer memory</subject><subject>Computer Science</subject><subject>Computing costs</subject><subject>Computing time</subject><subject>Concurrency</subject><subject>Concurrent processing</subject><subject>Control systems</subject><subject>Distributed, Parallel, and Cluster Computing</subject><subject>Dynamic control</subject><subject>Feedback control</subject><subject>Locks</subject><subject>Mapping</subject><subject>Microprocessors</subject><subject>Parallel programming</subject><subject>parallelism</subject><subject>synchronisation</subject><subject>thread mapping</subject><subject>Time synchronization</subject><subject>transactional memory</subject><issn>1532-0626</issn><issn>1532-0634</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><recordid>eNp1kE1OwzAQhS0EEqUgcQRLbGCR4t-kWVZVoUiVYAFry3XsNlUSB9sBdccROCMnwWlQd6zmzdM3o5kHwDVGE4wQuVetnjCO0hMwwpySBKWUnR41Sc_Bhfc7hDBGFI_AZtZA2QXb2LpUP1_fytZtF8pmA2XbOivVFtoG1rHpvbB1WhYeBgvrrgrlYcBpD4110FsTPqXTMDjZeKlCaRtZwVrX1u0vwZmRlddXf3UM3h4Wr_Nlsnp-fJrPVomiJEsTxTHRGeUIr3PNp4ZESaQuppgoapimBU_5eo2NyTJtCoJkTonSbIoZ0pwxOgZ3w96trETrylq6vbCyFMvZSvQewhkjaY4-cGRvBjY--t5pH8TOdi7e7AVBOSEZTTGJ1O1AKWe9d9oc12Ik-shFjFz0kUc0GdDPstL7fzkxf1kc-F9R6oQ3</recordid><startdate>20180925</startdate><enddate>20180925</enddate><creator>Zhou, Naweiluo</creator><creator>Delaval, Gwenaël</creator><creator>Robu, Bogdan</creator><creator>Rutten, Éric</creator><creator>Méhaut, Jean‐François</creator><general>Wiley Subscription Services, Inc</general><general>Wiley</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>1XC</scope><orcidid>https://orcid.org/0000-0001-9329-4500</orcidid><orcidid>https://orcid.org/0000-0003-1047-7462</orcidid><orcidid>https://orcid.org/0009-0000-3029-7384</orcidid><orcidid>https://orcid.org/0000-0001-8696-8212</orcidid><orcidid>https://orcid.org/0000-0001-7568-007X</orcidid></search><sort><creationdate>20180925</creationdate><title>An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory</title><author>Zhou, Naweiluo ; Delaval, Gwenaël ; Robu, Bogdan ; Rutten, Éric ; Méhaut, Jean‐François</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3276-c512e73501b9e58f23502aed812c3f4e3d565bb1ff77efd20a932ce48140e5443</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Access time</topic><topic>autonomic computing</topic><topic>Computer architecture</topic><topic>Computer memory</topic><topic>Computer Science</topic><topic>Computing costs</topic><topic>Computing time</topic><topic>Concurrency</topic><topic>Concurrent processing</topic><topic>Control systems</topic><topic>Distributed, Parallel, and Cluster Computing</topic><topic>Dynamic control</topic><topic>Feedback control</topic><topic>Locks</topic><topic>Mapping</topic><topic>Microprocessors</topic><topic>Parallel programming</topic><topic>parallelism</topic><topic>synchronisation</topic><topic>thread mapping</topic><topic>Time synchronization</topic><topic>transactional memory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zhou, Naweiluo</creatorcontrib><creatorcontrib>Delaval, Gwenaël</creatorcontrib><creatorcontrib>Robu, Bogdan</creatorcontrib><creatorcontrib>Rutten, Éric</creatorcontrib><creatorcontrib>Méhaut, Jean‐François</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Hyper Article en Ligne (HAL)</collection><jtitle>Concurrency and computation</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Zhou, Naweiluo</au><au>Delaval, Gwenaël</au><au>Robu, Bogdan</au><au>Rutten, Éric</au><au>Méhaut, Jean‐François</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory</atitle><jtitle>Concurrency and computation</jtitle><date>2018-09-25</date><risdate>2018</risdate><volume>30</volume><issue>18</issue><epage>n/a</epage><issn>1532-0626</issn><eissn>1532-0634</eissn><abstract>Summary
A parallel program needs to manage the trade‐off between the time spent in synchronisation and computation. This trade‐off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well‐mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time.</abstract><cop>Hoboken</cop><pub>Wiley Subscription Services, Inc</pub><doi>10.1002/cpe.4506</doi><tpages>1</tpages><orcidid>https://orcid.org/0000-0001-9329-4500</orcidid><orcidid>https://orcid.org/0000-0003-1047-7462</orcidid><orcidid>https://orcid.org/0009-0000-3029-7384</orcidid><orcidid>https://orcid.org/0000-0001-8696-8212</orcidid><orcidid>https://orcid.org/0000-0001-7568-007X</orcidid></addata></record> |
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subjects | Access time autonomic computing Computer architecture Computer memory Computer Science Computing costs Computing time Concurrency Concurrent processing Control systems Distributed, Parallel, and Cluster Computing Dynamic control Feedback control Locks Mapping Microprocessors Parallel programming parallelism synchronisation thread mapping Time synchronization transactional memory |
title | An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory |
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