Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

► We designed an NVSRAM cell with 22 nm FDSOI PDK for CMOS and HfO2 OxRRAMs. ► We showed that our NVSRAM cell is operational at high speed (20ns) and low voltage (1.5V). ► We presented the first analysis of VT variability on the stability of an 8T2R NV-SRAM. ► We showed that ROFF/RON of 10 is necess...

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Bibliographic Details
Published in:Solid-state electronics 2013-12, Vol.90, p.99-106
Main Authors: Hraziia, Makosiej, Adam, Palma, Giorgio, Portal, Jean-Michel, Bocquet, Marc, Thomas, Olivier, Clermidy, Fabien, Reyboz, Marina, Onkaraiah, Santhosh, Muller, Christophe, Deleruyelle, Damien, Vladimirescu, Andrei, Amara, Amara, Anghel, Costin
Format: Article
Language:English
Subjects:
Applied sciences
Data storage
Design. Technologies. Operation analysis. Testing
Electric potential
Electronics
Engineering Sciences
Exact sciences and technology
FDSOI
Hafnium oxide
Integrated circuits
Integrated circuits by function (including memories and processors)
Low leakage
Low power
Magnetic and optical mass memories
Memory devices
Micro and nanotechnologies
Microelectronics
Non-Volatile
NV-SRAM
Oxides
Power consumption
Resistive RAMs
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Static random access memory
Storage and reproduction of information
Transistors
Voltage
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Summary:► We designed an NVSRAM cell with 22 nm FDSOI PDK for CMOS and HfO2 OxRRAMs. ► We showed that our NVSRAM cell is operational at high speed (20ns) and low voltage (1.5V). ► We presented the first analysis of VT variability on the stability of an 8T2R NV-SRAM. ► We showed that ROFF/RON of 10 is necessary to have sufficient reliability of RESTORE. This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20ns) for the operating voltage of 1.0V. The information is backed-up during POWER-DOWN/RESTORE cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22nm FDSOI technology and resistive memory devices based on HfO2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high ROFF/RON is necessary to ensure reliable RESTORE operation and high SRAM yield under cell area and power consumption constraints.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2013.02.045