Full split C–V method for parameter extraction in ultra thin BOX FDSOI MOS devices

•We emphasize usefulness of gate-to-bulk capacitance (Cgb) in UTBB FDSOI.•Cgb configuration in FDSOI devices can provide detail substrate information.•TCAD and an improved coupling model confirmed our parameter extraction.•This method can be useful to assess full gate-stack without destructive analy...

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Bibliographic Details
Published in:Solid-state electronics 2014-09, Vol.99, p.104-107
Main Authors: Shin, Minju, Shi, Ming, Mouis, Mireille, Cros, Antoine, Josse, Emmanuel, Kim, Gyu-Tae, Ghibaudo, Gérard
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
Compound structure devices
Devices
Electronics
Engineering Sciences
Exact sciences and technology
Extraction
Feasibility
Gates
Micro and nanotechnologies
Microelectronics
MOS
MOS devices
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
SOI
Split CV
Stacks
UTBB
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Summary:•We emphasize usefulness of gate-to-bulk capacitance (Cgb) in UTBB FDSOI.•Cgb configuration in FDSOI devices can provide detail substrate information.•TCAD and an improved coupling model confirmed our parameter extraction.•This method can be useful to assess full gate-stack without destructive analysis. The feasibility of full split C–V method in ultra-thin body and BOX (UTBB) FDSOI devices is demonstrated, emphasizing the usefulness of gate-to-bulk capacitance. The split C–V measurements carried out on both gate-to-channel and gate-to-bulk mode are shown to be consistent with TCAD simulation. This enabled us to propose an improved parameter extraction methodology for the whole vertical FDSOI stack from gate to substrate using back biasing effect.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2014.04.039