Loading…

Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities

In this work a discussion on the estimated volume trap densities (N T ) compared to surface traps densities (N eff ) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of...

Full description

Saved in:
Bibliographic Details
Main Authors: Cretu, Bogdan, Nafaa, Beya, Simoen, Eddy, Hellings, Geert, Linten, Dimitri, Claeys, Cor
Format: Conference Proceeding
Language:English
Subjects:
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 1372
container_issue 24
container_start_page 1372
container_title
container_volume MA2020-01
creator Cretu, Bogdan
Nafaa, Beya
Simoen, Eddy
Hellings, Geert
Linten, Dimitri
Claeys, Cor
description In this work a discussion on the estimated volume trap densities (N T ) compared to surface traps densities (N eff ) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A 0i and t 0i related to the same trap, without any other assumption, a surface trap density of 2.8∙10 12 cm -2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙10 18 eV -1 cm -3 is obtained at 300 K. However, as the traps in the Si film are related to a volume phenomenon, two methodologies to estimate the volume trap densities are employed: one using the relationship between the surface trap density and volume trap densitiy [4], where B is a coefficient estimated to be 1/3 [4,5]; and a second one from the temperature (T) evolution at fixed frequency of the Lorentzian plateau level associated to the same trap (from equation 34 in [4]). Using the first method leads to a volume trap density of T4 of about 1.7∙10 19 cm -3 . The second method consists to use the maximum of the measured S vg_Lor ( f 0 ,T) dependence with temperature. Indeed, the S vg_Lor ( f 0 ,T) of Lorentzians associated to the same trap are proportional with t i (T)/{1 + [2p f 0 t i (T)] 2 }. For a given frequency f 0 , if 2p f 0 t i (T) ≫ 1, S Vg_Lor ( f 0 ,T) ∝ t i (T)] -1 , and S Vg_Lor ( f 0 ,T) increases with increasing temperature because t i decreases. If 2p f 0 t i (T) ≪ 1, then S Vg_Lor ( f 0 ,T) ∝ t i (T) and S Vg_Lor ( f 0 ,T) decreases with increasing temperature, as explained in detail in [4]. The evolution of the S vg_Lor ( f 0 ,T)∙ f 0 in a temperature range where T4 traps are active is illustrated in Figure 1 and presents a bell-shaped behavior, as expected. Using this method, volume trap densities of about 1.25∙10 18 cm -3 for f 0 = 10 kHz and of about 1.1∙10 18 cm -3 for f 0 = 14 kHz are obtained. It may be observed that the estimated volume trap densities of the T4 defect are
doi_str_mv 10.1149/MA2020-01241372mtgabs
format conference_proceeding
fullrecord <record><control><sourceid>hal_cross</sourceid><recordid>TN_cdi_hal_primary_oai_HAL_hal_02934726v1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>oai_HAL_hal_02934726v1</sourcerecordid><originalsourceid>FETCH-LOGICAL-c801-4f047b6fe2da76f2c302f24631db7c6e2f8c20022f1e708aa84110c5987fe41f3</originalsourceid><addsrcrecordid>eNpVkE9LAzEQxYMoWKsfQcjVw-pkkv1Tb6W1trDFQ0uvS5qdtJFutyS7gt_erSsFYWDeDO_3Do-xRwHPQqjRy3KMgBCBQCVkilWz09twxQYoYhEhyPj6opW8ZXchfALILEMcsDB1wbQhuPrIu2n2xGdu13oKvLZ8Sd41Z7Eo6dg466jka69Pgee10U13uZ5ZuQ47VK981XqrDfEN-dAGvqkPbUW_DJ_SMbjGUbhnN1YfAj387SFbz97Wk3mUf7wvJuM8MhmISFlQ6TaxhKVOE4tGAlpUiRTlNjUJoc0MAiBaQSlkWmdKCDDxKEstKWHlkD31sXt9KE7eVdp_F7V2xXycF-cf4EiqFJMv0Xnj3mt8HYInewEEFOeSi77k4n_J8gex93Du</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities</title><source>Alma/SFX Local Collection</source><creator>Cretu, Bogdan ; Nafaa, Beya ; Simoen, Eddy ; Hellings, Geert ; Linten, Dimitri ; Claeys, Cor</creator><creatorcontrib>Cretu, Bogdan ; Nafaa, Beya ; Simoen, Eddy ; Hellings, Geert ; Linten, Dimitri ; Claeys, Cor</creatorcontrib><description>In this work a discussion on the estimated volume trap densities (N T ) compared to surface traps densities (N eff ) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A 0i and t 0i related to the same trap, without any other assumption, a surface trap density of 2.8∙10 12 cm -2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙10 18 eV -1 cm -3 is obtained at 300 K. However, as the traps in the Si film are related to a volume phenomenon, two methodologies to estimate the volume trap densities are employed: one using the relationship between the surface trap density and volume trap densitiy [4], where B is a coefficient estimated to be 1/3 [4,5]; and a second one from the temperature (T) evolution at fixed frequency of the Lorentzian plateau level associated to the same trap (from equation 34 in [4]). Using the first method leads to a volume trap density of T4 of about 1.7∙10 19 cm -3 . The second method consists to use the maximum of the measured S vg_Lor ( f 0 ,T) dependence with temperature. Indeed, the S vg_Lor ( f 0 ,T) of Lorentzians associated to the same trap are proportional with t i (T)/{1 + [2p f 0 t i (T)] 2 }. For a given frequency f 0 , if 2p f 0 t i (T) ≫ 1, S Vg_Lor ( f 0 ,T) ∝ t i (T)] -1 , and S Vg_Lor ( f 0 ,T) increases with increasing temperature because t i decreases. If 2p f 0 t i (T) ≪ 1, then S Vg_Lor ( f 0 ,T) ∝ t i (T) and S Vg_Lor ( f 0 ,T) decreases with increasing temperature, as explained in detail in [4]. The evolution of the S vg_Lor ( f 0 ,T)∙ f 0 in a temperature range where T4 traps are active is illustrated in Figure 1 and presents a bell-shaped behavior, as expected. Using this method, volume trap densities of about 1.25∙10 18 cm -3 for f 0 = 10 kHz and of about 1.1∙10 18 cm -3 for f 0 = 14 kHz are obtained. It may be observed that the estimated volume trap densities of the T4 defect are about one decade lower than when using the first method. This overestimation by the first method is related to the fact that the theoretical B coefficient was determined for conventional planar devices with one gate [4,5]. Moreover, it may be noticed that the second method is dependent on the fixed f 0 selected. The paper will present a discussion with more details, considering all identified traps in [1] and considering additional new low frequency noise spectroscopy results. References : [1] Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson et al., “Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology”, in Tech. Dig. Symp. on VLSI Technology, The IEEE New York, 2018, p.p. 85-86, DOI: 10.1109/VLSIT.2018.8510654. [2] Boudier, B. Cretu, E. Simoen, R. Carin, A. Veloso, N. Collaert, and A. Thean, “Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology,” Solid State Electron., vol. 128, pp. 102-108, 2017, DOI: 10.1016/j.sse.2016.10.012. [3] Boudier, B. Cretu, E. Simoen, G. Hellings, T. Schram, H. Mertens and D. Linten, “Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs”, In Proceedings of EUROSOI-ULIS’2019. [4] Lukyanchikova, “Noise and Fluctuations Control in Electronic Device”, edited by A. Balandin, American Scientific, Riverside, CA, 2002, pp. 201-233. [5] Yau and C-T. Sah, “Theory and experiments of low-frequency generation-recombination noise in MOS transistors”, IEEE Trans. Electron Dev., 1969, vol.16, pp. 170-177. Figure 1 : S Vg_Lor ( f 0 ,T)· f 0 versus temperature for the T4 trap identified in [3]; on the secondary Oy axis the characteristic frequency f 0i of the Lorentzians is displayed in function of temperature. Figure 1</description><identifier>ISSN: 2151-2043</identifier><identifier>ISSN: 1091-8213</identifier><identifier>EISSN: 2151-2035</identifier><identifier>DOI: 10.1149/MA2020-01241372mtgabs</identifier><language>eng</language><publisher>IOP Publishing</publisher><subject>Engineering Sciences ; Micro and nanotechnologies ; Microelectronics</subject><ispartof>ECS Meeting Abstracts, 2020, Vol.MA2020-01 (24), p.1372-1372</ispartof><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>230,309,310,776,780,785,786,881,23909,23910,25118,27902</link.rule.ids><backlink>$$Uhttps://hal.science/hal-02934726$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Cretu, Bogdan</creatorcontrib><creatorcontrib>Nafaa, Beya</creatorcontrib><creatorcontrib>Simoen, Eddy</creatorcontrib><creatorcontrib>Hellings, Geert</creatorcontrib><creatorcontrib>Linten, Dimitri</creatorcontrib><creatorcontrib>Claeys, Cor</creatorcontrib><title>Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities</title><title>ECS Meeting Abstracts</title><description>In this work a discussion on the estimated volume trap densities (N T ) compared to surface traps densities (N eff ) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A 0i and t 0i related to the same trap, without any other assumption, a surface trap density of 2.8∙10 12 cm -2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙10 18 eV -1 cm -3 is obtained at 300 K. However, as the traps in the Si film are related to a volume phenomenon, two methodologies to estimate the volume trap densities are employed: one using the relationship between the surface trap density and volume trap densitiy [4], where B is a coefficient estimated to be 1/3 [4,5]; and a second one from the temperature (T) evolution at fixed frequency of the Lorentzian plateau level associated to the same trap (from equation 34 in [4]). Using the first method leads to a volume trap density of T4 of about 1.7∙10 19 cm -3 . The second method consists to use the maximum of the measured S vg_Lor ( f 0 ,T) dependence with temperature. Indeed, the S vg_Lor ( f 0 ,T) of Lorentzians associated to the same trap are proportional with t i (T)/{1 + [2p f 0 t i (T)] 2 }. For a given frequency f 0 , if 2p f 0 t i (T) ≫ 1, S Vg_Lor ( f 0 ,T) ∝ t i (T)] -1 , and S Vg_Lor ( f 0 ,T) increases with increasing temperature because t i decreases. If 2p f 0 t i (T) ≪ 1, then S Vg_Lor ( f 0 ,T) ∝ t i (T) and S Vg_Lor ( f 0 ,T) decreases with increasing temperature, as explained in detail in [4]. The evolution of the S vg_Lor ( f 0 ,T)∙ f 0 in a temperature range where T4 traps are active is illustrated in Figure 1 and presents a bell-shaped behavior, as expected. Using this method, volume trap densities of about 1.25∙10 18 cm -3 for f 0 = 10 kHz and of about 1.1∙10 18 cm -3 for f 0 = 14 kHz are obtained. It may be observed that the estimated volume trap densities of the T4 defect are about one decade lower than when using the first method. This overestimation by the first method is related to the fact that the theoretical B coefficient was determined for conventional planar devices with one gate [4,5]. Moreover, it may be noticed that the second method is dependent on the fixed f 0 selected. The paper will present a discussion with more details, considering all identified traps in [1] and considering additional new low frequency noise spectroscopy results. References : [1] Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson et al., “Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology”, in Tech. Dig. Symp. on VLSI Technology, The IEEE New York, 2018, p.p. 85-86, DOI: 10.1109/VLSIT.2018.8510654. [2] Boudier, B. Cretu, E. Simoen, R. Carin, A. Veloso, N. Collaert, and A. Thean, “Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology,” Solid State Electron., vol. 128, pp. 102-108, 2017, DOI: 10.1016/j.sse.2016.10.012. [3] Boudier, B. Cretu, E. Simoen, G. Hellings, T. Schram, H. Mertens and D. Linten, “Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs”, In Proceedings of EUROSOI-ULIS’2019. [4] Lukyanchikova, “Noise and Fluctuations Control in Electronic Device”, edited by A. Balandin, American Scientific, Riverside, CA, 2002, pp. 201-233. [5] Yau and C-T. Sah, “Theory and experiments of low-frequency generation-recombination noise in MOS transistors”, IEEE Trans. Electron Dev., 1969, vol.16, pp. 170-177. Figure 1 : S Vg_Lor ( f 0 ,T)· f 0 versus temperature for the T4 trap identified in [3]; on the secondary Oy axis the characteristic frequency f 0i of the Lorentzians is displayed in function of temperature. Figure 1</description><subject>Engineering Sciences</subject><subject>Micro and nanotechnologies</subject><subject>Microelectronics</subject><issn>2151-2043</issn><issn>1091-8213</issn><issn>2151-2035</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2020</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNpVkE9LAzEQxYMoWKsfQcjVw-pkkv1Tb6W1trDFQ0uvS5qdtJFutyS7gt_erSsFYWDeDO_3Do-xRwHPQqjRy3KMgBCBQCVkilWz09twxQYoYhEhyPj6opW8ZXchfALILEMcsDB1wbQhuPrIu2n2xGdu13oKvLZ8Sd41Z7Eo6dg466jka69Pgee10U13uZ5ZuQ47VK981XqrDfEN-dAGvqkPbUW_DJ_SMbjGUbhnN1YfAj387SFbz97Wk3mUf7wvJuM8MhmISFlQ6TaxhKVOE4tGAlpUiRTlNjUJoc0MAiBaQSlkWmdKCDDxKEstKWHlkD31sXt9KE7eVdp_F7V2xXycF-cf4EiqFJMv0Xnj3mt8HYInewEEFOeSi77k4n_J8gex93Du</recordid><startdate>20200501</startdate><enddate>20200501</enddate><creator>Cretu, Bogdan</creator><creator>Nafaa, Beya</creator><creator>Simoen, Eddy</creator><creator>Hellings, Geert</creator><creator>Linten, Dimitri</creator><creator>Claeys, Cor</creator><general>IOP Publishing</general><scope>AAYXX</scope><scope>CITATION</scope><scope>1XC</scope></search><sort><creationdate>20200501</creationdate><title>Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities</title><author>Cretu, Bogdan ; Nafaa, Beya ; Simoen, Eddy ; Hellings, Geert ; Linten, Dimitri ; Claeys, Cor</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c801-4f047b6fe2da76f2c302f24631db7c6e2f8c20022f1e708aa84110c5987fe41f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Engineering Sciences</topic><topic>Micro and nanotechnologies</topic><topic>Microelectronics</topic><toplevel>online_resources</toplevel><creatorcontrib>Cretu, Bogdan</creatorcontrib><creatorcontrib>Nafaa, Beya</creatorcontrib><creatorcontrib>Simoen, Eddy</creatorcontrib><creatorcontrib>Hellings, Geert</creatorcontrib><creatorcontrib>Linten, Dimitri</creatorcontrib><creatorcontrib>Claeys, Cor</creatorcontrib><collection>CrossRef</collection><collection>Hyper Article en Ligne (HAL)</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Cretu, Bogdan</au><au>Nafaa, Beya</au><au>Simoen, Eddy</au><au>Hellings, Geert</au><au>Linten, Dimitri</au><au>Claeys, Cor</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities</atitle><btitle>ECS Meeting Abstracts</btitle><date>2020-05-01</date><risdate>2020</risdate><volume>MA2020-01</volume><issue>24</issue><spage>1372</spage><epage>1372</epage><pages>1372-1372</pages><issn>2151-2043</issn><issn>1091-8213</issn><eissn>2151-2035</eissn><abstract>In this work a discussion on the estimated volume trap densities (N T ) compared to surface traps densities (N eff ) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A 0i and t 0i related to the same trap, without any other assumption, a surface trap density of 2.8∙10 12 cm -2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙10 18 eV -1 cm -3 is obtained at 300 K. However, as the traps in the Si film are related to a volume phenomenon, two methodologies to estimate the volume trap densities are employed: one using the relationship between the surface trap density and volume trap densitiy [4], where B is a coefficient estimated to be 1/3 [4,5]; and a second one from the temperature (T) evolution at fixed frequency of the Lorentzian plateau level associated to the same trap (from equation 34 in [4]). Using the first method leads to a volume trap density of T4 of about 1.7∙10 19 cm -3 . The second method consists to use the maximum of the measured S vg_Lor ( f 0 ,T) dependence with temperature. Indeed, the S vg_Lor ( f 0 ,T) of Lorentzians associated to the same trap are proportional with t i (T)/{1 + [2p f 0 t i (T)] 2 }. For a given frequency f 0 , if 2p f 0 t i (T) ≫ 1, S Vg_Lor ( f 0 ,T) ∝ t i (T)] -1 , and S Vg_Lor ( f 0 ,T) increases with increasing temperature because t i decreases. If 2p f 0 t i (T) ≪ 1, then S Vg_Lor ( f 0 ,T) ∝ t i (T) and S Vg_Lor ( f 0 ,T) decreases with increasing temperature, as explained in detail in [4]. The evolution of the S vg_Lor ( f 0 ,T)∙ f 0 in a temperature range where T4 traps are active is illustrated in Figure 1 and presents a bell-shaped behavior, as expected. Using this method, volume trap densities of about 1.25∙10 18 cm -3 for f 0 = 10 kHz and of about 1.1∙10 18 cm -3 for f 0 = 14 kHz are obtained. It may be observed that the estimated volume trap densities of the T4 defect are about one decade lower than when using the first method. This overestimation by the first method is related to the fact that the theoretical B coefficient was determined for conventional planar devices with one gate [4,5]. Moreover, it may be noticed that the second method is dependent on the fixed f 0 selected. The paper will present a discussion with more details, considering all identified traps in [1] and considering additional new low frequency noise spectroscopy results. References : [1] Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson et al., “Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology”, in Tech. Dig. Symp. on VLSI Technology, The IEEE New York, 2018, p.p. 85-86, DOI: 10.1109/VLSIT.2018.8510654. [2] Boudier, B. Cretu, E. Simoen, R. Carin, A. Veloso, N. Collaert, and A. Thean, “Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology,” Solid State Electron., vol. 128, pp. 102-108, 2017, DOI: 10.1016/j.sse.2016.10.012. [3] Boudier, B. Cretu, E. Simoen, G. Hellings, T. Schram, H. Mertens and D. Linten, “Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs”, In Proceedings of EUROSOI-ULIS’2019. [4] Lukyanchikova, “Noise and Fluctuations Control in Electronic Device”, edited by A. Balandin, American Scientific, Riverside, CA, 2002, pp. 201-233. [5] Yau and C-T. Sah, “Theory and experiments of low-frequency generation-recombination noise in MOS transistors”, IEEE Trans. Electron Dev., 1969, vol.16, pp. 170-177. Figure 1 : S Vg_Lor ( f 0 ,T)· f 0 versus temperature for the T4 trap identified in [3]; on the secondary Oy axis the characteristic frequency f 0i of the Lorentzians is displayed in function of temperature. Figure 1</abstract><pub>IOP Publishing</pub><doi>10.1149/MA2020-01241372mtgabs</doi><tpages>1</tpages></addata></record>
fulltext fulltext
identifier ISSN: 2151-2043
ispartof ECS Meeting Abstracts, 2020, Vol.MA2020-01 (24), p.1372-1372
issn 2151-2043
1091-8213
2151-2035
language eng
recordid cdi_hal_primary_oai_HAL_hal_02934726v1
source Alma/SFX Local Collection
subjects Engineering Sciences
Micro and nanotechnologies
Microelectronics
title Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T02%3A31%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-hal_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Discussion%20on%20the%20Figures%20of%20Merit%20of%20Identified%20Traps%20Located%20in%20the%20Si%20Film:%20Surface%20Versus%20Volume%20Trap%20Densities&rft.btitle=ECS%20Meeting%20Abstracts&rft.au=Cretu,%20Bogdan&rft.date=2020-05-01&rft.volume=MA2020-01&rft.issue=24&rft.spage=1372&rft.epage=1372&rft.pages=1372-1372&rft.issn=2151-2043&rft.eissn=2151-2035&rft_id=info:doi/10.1149/MA2020-01241372mtgabs&rft_dat=%3Chal_cross%3Eoai_HAL_hal_02934726v1%3C/hal_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c801-4f047b6fe2da76f2c302f24631db7c6e2f8c20022f1e708aa84110c5987fe41f3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true