From defects creation to circuit reliability – A bottom-up approach (invited)

• Published in: Microelectronic engineering 2011-07, Vol.88 (7), p.1396-1407
• Main Authors: Huard, V., Cacho, F., Mamy Randriamihaja, Y., Bravaix, A.
• Format: Article
• Language: English
• Subjects: Applied sciences; Assessments; Bias temperature stress; Border traps; Carriers; Channel cold carriers; Channels; Circuit properties; Circuit reliability; Damage; Design-in Reliability; Device lifetime; Devices; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Engineering Sciences; Exact sciences and technology; Fractures; Ground state; Hot-Carrier degradation; Interface traps generation; Interfaces; Mechanical properties and methods of testing. Rheology. Fracture mechanics. Tribology; Metals. Metallurgy; MOSFETs; Multi vibrational excitation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Spice models; Transistors; Trapped oxide charges; Ultra-thin gate-oxide
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2011.03.101

This paper presents a theoretical framework about interface states creation rate from Si–H bonds at the Si/SiO 2 interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two others cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows us physically modeling the reliability of MOSFET transistors, and particularly NBTI permanent part, and Channel Hot Carrier (CHC) to Cold Carrier (CCC) damage. Finally, the translation of these physical models into reliability spice models is discussed. These models pave the way to Design-in Reliability (DiR) approach which seeks to provide a quantitative assessment of reliability – CMOS device reliability in this case – at design stage thereby enabling judicious margins to be taken beforehand.