Hardware Acceleration of SIKE on Low-End FPGAs

In this letter, we present the design and implementation results of two hardware accelerators for the supersingular isogeny key encapsulation (SIKE) suite. These designs aim at enabling quantum-safe cryptography solutions for constrained platforms by offloading the cost of bulk arithmetic from the m...

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Bibliographic Details
Published in:IEEE embedded systems letters 2023-06, Vol.15 (2), p.73-76
Main Authors: Lara-Nino, Carlos Andres, Diaz-Perez, Arturo, Morales-Sandoval, Miguel
Format: Article
Language:English
Subjects:
Accelerators
Arithmetic
Co-design
Complexity theory
Computer Science
Coprocessor
Cryptography
Energy consumption
Engineering Sciences
Field programmable gate arrays
field-programmable gate array (FPGA)
Hardware
hardware/software co-design
low area
low energy
Mathematics
Microprocessors
Public key
Registers
Signal processing algorithms
Software
supersingular isogeny key encapsulation (SIKE)
Table lookup
VHDL
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Summary:In this letter, we present the design and implementation results of two hardware accelerators for the supersingular isogeny key encapsulation (SIKE) suite. These designs aim at enabling quantum-safe cryptography solutions for constrained platforms by offloading the cost of bulk arithmetic from the main processor. One of the proposed architectures has area reduction as the main implementation goal; the second design improves the former on the energy footprint. This software-hardware co-design addresses the challenges of performing bulk arithmetic in software and reducing the control complexity in hardware, thus minimizing the communication overheads found on simple arithmetic accelerators. Compared to other designs in the literature, the proposed architectures do not rely on in-fabric memory and processing units, a key point for porting such solutions to any implementation technology such as field-programmable gate arrays (FPGAs).
ISSN:1943-0663
1943-0671
DOI:10.1109/LES.2022.3175016