Some optimizations of hardware multiplication by constant matrices

This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recodin...

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Published in:IEEE transactions on computers 2005-10, Vol.54 (10), p.1271-1282
Main Authors: Boullis, N., Tisserand, A.
Format: Article
Language:English
Subjects:
Algorithms
common subexpressions sharing
Computer Arithmetic
Computer Science
Digital arithmetic
Field programmable gate arrays
FIR digital filters
FIR filter
Generators
Hardware
Hardware design languages
Index Terms- Computer arithmetic
Mathematical analysis
Matrices
Matrix methods
Matrix multiplication
Multiplication
multiplication by constants
Optimization
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cited_by cdi_FETCH-LOGICAL-c416t-74cc485f50f062a81b1f4467c0f65b4865a9a45c91ed4f8d0013ebf671d007613
cites cdi_FETCH-LOGICAL-c416t-74cc485f50f062a81b1f4467c0f65b4865a9a45c91ed4f8d0013ebf671d007613
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creator Boullis, N.
Tisserand, A.
description This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.
doi_str_mv 10.1109/TC.2005.168
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fullrecord <record><control><sourceid>proquest_hal_p</sourceid><recordid>TN_cdi_hal_primary_oai_HAL_lirmm_00113092v1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1501792</ieee_id><sourcerecordid>2351750291</sourcerecordid><originalsourceid>FETCH-LOGICAL-c416t-74cc485f50f062a81b1f4467c0f65b4865a9a45c91ed4f8d0013ebf671d007613</originalsourceid><addsrcrecordid>eNp90TFPAyEYBmBiNLFWJ0eXi4MO5urHHXAw1otakyYO1plQCinNXalw1dRfL7XGJg5OkPAAL7wInWMYYAzidlIPCgA6wIwfoB6mtMqFoOwQ9QAwz0VJ4BidxLgAAFaA6KG7F9-azK8617pP1Tm_jJm32VyF2YcKJmvXTedWjdPfa9l0k-lEOrXsslZ1wWkTT9GRVU00Zz9jH70-3E_qUT5-fnyqh-NcE8y6vCJaE04tBZvuVhxPsSWEVRoso1PCGVVCEaoFNjNi-SwlLs3UsgqnacVw2Uc3u3PnqpGr4FoVNtIrJ0fDsWxcaFuZ9uASRPG-1dc7vQr-bW1iJ1sXtWkatTR-HSUXrChLWpEkr_6VBcdQ8FIkePkHLvw6LNObJWcVhfS7dJ9SBx9jMPY3Kga5LUlOarktSaaSkr7YaWeM2UsKuBJF-QU8YIrt</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>867503405</pqid></control><display><type>article</type><title>Some optimizations of hardware multiplication by constant matrices</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Boullis, N. ; Tisserand, A.</creator><creatorcontrib>Boullis, N. ; Tisserand, A.</creatorcontrib><description>This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.</description><identifier>ISSN: 0018-9340</identifier><identifier>EISSN: 1557-9956</identifier><identifier>DOI: 10.1109/TC.2005.168</identifier><identifier>CODEN: ITCOB4</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; common subexpressions sharing ; Computer Arithmetic ; Computer Science ; Digital arithmetic ; Field programmable gate arrays ; FIR digital filters ; FIR filter ; Generators ; Hardware ; Hardware design languages ; Index Terms- Computer arithmetic ; Mathematical analysis ; Matrices ; Matrix methods ; Matrix multiplication ; Multiplication ; multiplication by constants ; Optimization</subject><ispartof>IEEE transactions on computers, 2005-10, Vol.54 (10), p.1271-1282</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005</rights><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c416t-74cc485f50f062a81b1f4467c0f65b4865a9a45c91ed4f8d0013ebf671d007613</citedby><cites>FETCH-LOGICAL-c416t-74cc485f50f062a81b1f4467c0f65b4865a9a45c91ed4f8d0013ebf671d007613</cites><orcidid>0000-0001-7042-3541</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1501792$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,314,780,784,885,27924,27925,54796</link.rule.ids><backlink>$$Uhttps://hal-lirmm.ccsd.cnrs.fr/lirmm-00113092$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Boullis, N.</creatorcontrib><creatorcontrib>Tisserand, A.</creatorcontrib><title>Some optimizations of hardware multiplication by constant matrices</title><title>IEEE transactions on computers</title><addtitle>TC</addtitle><description>This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.</description><subject>Algorithms</subject><subject>common subexpressions sharing</subject><subject>Computer Arithmetic</subject><subject>Computer Science</subject><subject>Digital arithmetic</subject><subject>Field programmable gate arrays</subject><subject>FIR digital filters</subject><subject>FIR filter</subject><subject>Generators</subject><subject>Hardware</subject><subject>Hardware design languages</subject><subject>Index Terms- Computer arithmetic</subject><subject>Mathematical analysis</subject><subject>Matrices</subject><subject>Matrix methods</subject><subject>Matrix multiplication</subject><subject>Multiplication</subject><subject>multiplication by constants</subject><subject>Optimization</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2005</creationdate><recordtype>article</recordtype><recordid>eNp90TFPAyEYBmBiNLFWJ0eXi4MO5urHHXAw1otakyYO1plQCinNXalw1dRfL7XGJg5OkPAAL7wInWMYYAzidlIPCgA6wIwfoB6mtMqFoOwQ9QAwz0VJ4BidxLgAAFaA6KG7F9-azK8617pP1Tm_jJm32VyF2YcKJmvXTedWjdPfa9l0k-lEOrXsslZ1wWkTT9GRVU00Zz9jH70-3E_qUT5-fnyqh-NcE8y6vCJaE04tBZvuVhxPsSWEVRoso1PCGVVCEaoFNjNi-SwlLs3UsgqnacVw2Uc3u3PnqpGr4FoVNtIrJ0fDsWxcaFuZ9uASRPG-1dc7vQr-bW1iJ1sXtWkatTR-HSUXrChLWpEkr_6VBcdQ8FIkePkHLvw6LNObJWcVhfS7dJ9SBx9jMPY3Kga5LUlOarktSaaSkr7YaWeM2UsKuBJF-QU8YIrt</recordid><startdate>20051001</startdate><enddate>20051001</enddate><creator>Boullis, N.</creator><creator>Tisserand, A.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>F28</scope><scope>FR3</scope><scope>1XC</scope><scope>VOOES</scope><orcidid>https://orcid.org/0000-0001-7042-3541</orcidid></search><sort><creationdate>20051001</creationdate><title>Some optimizations of hardware multiplication by constant matrices</title><author>Boullis, N. ; Tisserand, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c416t-74cc485f50f062a81b1f4467c0f65b4865a9a45c91ed4f8d0013ebf671d007613</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Algorithms</topic><topic>common subexpressions sharing</topic><topic>Computer Arithmetic</topic><topic>Computer Science</topic><topic>Digital arithmetic</topic><topic>Field programmable gate arrays</topic><topic>FIR digital filters</topic><topic>FIR filter</topic><topic>Generators</topic><topic>Hardware</topic><topic>Hardware design languages</topic><topic>Index Terms- Computer arithmetic</topic><topic>Mathematical analysis</topic><topic>Matrices</topic><topic>Matrix methods</topic><topic>Matrix multiplication</topic><topic>Multiplication</topic><topic>multiplication by constants</topic><topic>Optimization</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Boullis, N.</creatorcontrib><creatorcontrib>Tisserand, A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) Online</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><collection>Hyper Article en Ligne (HAL)</collection><collection>Hyper Article en Ligne (HAL) (Open Access)</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Boullis, N.</au><au>Tisserand, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Some optimizations of hardware multiplication by constant matrices</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>2005-10-01</date><risdate>2005</risdate><volume>54</volume><issue>10</issue><spage>1271</spage><epage>1282</epage><pages>1271-1282</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TC.2005.168</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0001-7042-3541</orcidid><oa>free_for_read</oa></addata></record>
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1557-9956
language eng
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source IEEE Electronic Library (IEL) Journals
subjects Algorithms
common subexpressions sharing
Computer Arithmetic
Computer Science
Digital arithmetic
Field programmable gate arrays
FIR digital filters
FIR filter
Generators
Hardware
Hardware design languages
Index Terms- Computer arithmetic
Mathematical analysis
Matrices
Matrix methods
Matrix multiplication
Multiplication
multiplication by constants
Optimization
title Some optimizations of hardware multiplication by constant matrices
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T21%3A47%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_hal_p&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Some%20optimizations%20of%20hardware%20multiplication%20by%20constant%20matrices&rft.jtitle=IEEE%20transactions%20on%20computers&rft.au=Boullis,%20N.&rft.date=2005-10-01&rft.volume=54&rft.issue=10&rft.spage=1271&rft.epage=1282&rft.pages=1271-1282&rft.issn=0018-9340&rft.eissn=1557-9956&rft.coden=ITCOB4&rft_id=info:doi/10.1109/TC.2005.168&rft_dat=%3Cproquest_hal_p%3E2351750291%3C/proquest_hal_p%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c416t-74cc485f50f062a81b1f4467c0f65b4865a9a45c91ed4f8d0013ebf671d007613%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=867503405&rft_id=info:pmid/&rft_ieee_id=1501792&rfr_iscdi=true