Novel High-Speed Ternary Logic using Step-shaped Threshold Switch

We presented the ternary logic using a threshold switch (TS) that enabled faster operation than the existing ternary concept and quantitatively compared it to binary logic in a 5-nm node. TS-ternary inverter shows comparable power and performance to the binary inverter in low to high (high to low) o...

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Bibliographic Details
Published in:IEEE electron device letters 2023-03, Vol.44 (3), p.1-1
Main Authors: Lee, Junjong, Heo, Seongjae, Hwang, Hyunsang, Baek, Rock-Hyun
Format: Article
Language:English
Subjects:
Ag/HfO<sub xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">2
Delays
Inverters
Layout
Logic
Multivalued logic
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Ovonic threshold switch (OTS)
Power demand
Power Performance and Area (PPA)
Random access memory
Switches
Ternary
Threshold currents
Threshold Switch (TS)
Threshold voltage
Transistors
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Summary:We presented the ternary logic using a threshold switch (TS) that enabled faster operation than the existing ternary concept and quantitatively compared it to binary logic in a 5-nm node. TS-ternary inverter shows comparable power and performance to the binary inverter in low to high (high to low) operations. Operations passing through the middle state show large delays but still show the fastest speed among existing ternary concepts. Further, our TS-ternary can be applied to various logic applications, and the noise margin can be optimized by adjusting the threshold voltage of the transistor (V T,TR ) and threshold current of TS (I T ). Moreover, the ternary layout requires a slightly larger area, but the system complexity is reduced to 71.0 % compared with binary. Overall, TS-ternary logic is a promising candidate as a future ternary concept, having fast speed, high density, and applicability to diverse logic applications.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2023.3237385