A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

• Main Authors: Wu, Shien-Yang, Chang, C.H., Chiang, M.C., Lin, C.Y., Liaw, J.J., Cheng, J.Y., Yeh, J.Y., Chen, H.F., Chang, S.Y., Lai, K.T., Liang, M.S., Pan, K.H., Chen, J.H., Chang, V.S., Luo, T.C., Wang, X., Mor, Y.S., Lin, C.I., Wang, S.H., Hsieh, M.Y., Chen, C.Y., Wu, B.F., Lin, C.J., Liang, C.S., Tsao, C.P., Li, C.T., Chen, C.H., Hsieh, C.H., Liu, H.H., Chen, P.N., Chen, C.C., Chen, R., Yeo, Y.C., Chui, C.O., Chang, W., Lee, T.L., Huang, K.B., Lin, H.J., Chen, K.W., Tsai, M.H., Chen, K.S., Chen, X.M., Cheng, Y.K., Wang, C.H., Shue, W., Ku, Y., Jang, S. M., Cao, M., Lu, L.C., Chang, T.S.
• Format: Conference Proceeding
• Language: English
• Subjects: 5G mobile communication; FinFETs; Industries; Metals; Performance evaluation; Random access memory; Technological innovation
• ISSN: 2156-017X
• DOI: 10.1109/IEDM45625.2022.10019498

The industry fastest time-to-manufacturability 3nm CMOS platform technology is presented. FinFlex™ with standard cells consisting of different fin configurations is introduced for the first time to offer the critical design flexibility for better power efficiency and performance optimization compared to traditional FinFET technologies. An aggressive scaling of ~1.6X logic density increase, 18% speed improvement and 34% power reduction are achieved over our previous 5nm CMOS process. This FinFlex™ platform technology provides the best-in-class PPAC values to fully unleash product innovations in 5G and HPC applications.