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Inter-Layer Dielectric Engineering for Monolithic Stacking 4F2-2 T0C DRAM with Channel-All-Around (CAA) IGZO FET to Achieve Good Reliability (>104 s Bias Stress, >1012 Cycles Endurance)
To address the stacking requirement of 4F^{2}-2 T0C DRAM with vertical channel-all-around (CAA) IGZO FETs, for the first time, the effect of inter-layer dielectric (ILD) on CAA-IGZO FETs has been studied by varying dielectric material and process. By using optimized ILD and IGZO deposition cycle rat...
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Main Authors: | , , , , , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
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Summary: | To address the stacking requirement of 4F^{2}-2 T0C DRAM with vertical channel-all-around (CAA) IGZO FETs, for the first time, the effect of inter-layer dielectric (ILD) on CAA-IGZO FETs has been studied by varying dielectric material and process. By using optimized ILD and IGZO deposition cycle ratio, CAA-IGZO FET with high reliability is obtained. The optimized device exhibits a {V}_{th} shift of less than 25 mV after 10^{4}s bias stress and no significant degradation after 10 12 cycles endurance. Our results provide an important reference for facilitating the monolithic stacking of multilayer IGZO FETs to realize 3D DRAM. |
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ISSN: | 2156-017X |
DOI: | 10.1109/IEDM45625.2022.10019502 |