Investigation of the Off-State Degradation in Advanced FinFET Technology-Part I: Experiments and Analysis

Previous works on transistor reliability are mostly devoted to ON-state degradations, such as bias temperature instability and hot carrier degradation, for which physical models have been developed to describe corresponding mechanisms. However, very limited data on OFF-state degradation is available...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2023-03, Vol.70 (3), p.1-7
Main Authors: Sun, Zixuan, Wang, Zirui, Wang, Runsheng, Zhang, Lining, Zhang, Jiayang, Zhang, Zuodong, Song, Jiahao, Wang, Da, Ji, Zhigang, Huang, Ru
Format: Article
Language:English
Subjects:
Component reliability
Degradation
Electron traps
FinFET
FinFETs
Hole traps
Logic gates
mixed-mode degradation
MOS devices
OFF-state degradation
reliability
Reliability analysis
secondary carriers
Stress
Transistors
Tunneling
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Summary:Previous works on transistor reliability are mostly devoted to ON-state degradations, such as bias temperature instability and hot carrier degradation, for which physical models have been developed to describe corresponding mechanisms. However, very limited data on OFF-state degradation is available, especially in FinFET technology. In the first part of this article, OFF-sate degradations of 7-nm FinFET technology are reported for the first time. The physics mechanisms in OFF-state degradation are proposed by combining TCAD simulations and comprehensive experimental characterizations. It is found that an enhanced secondary carriers effect is responsible for the OFF-state degradation with contributions from both trapped electrons and holes. Furthermore, typical locations of electron traps and hole traps under the OFF-state degradation are identified. The abnormal leakage degradation is explained in a consistent manner. The analysis here leads to a compact reliability model reported in part II.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2023.3239585