A large, fast instruction window for tolerating cache misses

Instruction window size is an important design parameter for many modern processors. This paper presents a new instruction window design targeted at achieving the latency tolerance of large windows with the clock cycle time of small windows. The key observation is that instructions dependent on a lo...

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Bibliographic Details
Published in:Proceedings 29th Annual International Symposium on Computer Architecture 2002, p.59-70
Main Authors: Lebeck, A.R., Koppanalil, J., Tong Li, Patwardhan, J., Rotenberg, E.
Format: Article
Language:eng ; jpn
Subjects:
Clocks
Computer science
Degradation
Delay
Hardware
Logic
Microarchitecture
Microprocessors
Parallel processing
Time factors
Online Access:Request full text
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Summary:Instruction window size is an important design parameter for many modern processors. This paper presents a new instruction window design targeted at achieving the latency tolerance of large windows with the clock cycle time of small windows. The key observation is that instructions dependent on a long latency operation (e.g., cache miss) cannot execute until that source operation completes. These instructions are moved out of the conventional, small, issue queue to a much larger waiting instruction buffer (WIB). When the long latency operation completes, the instructions are reinserted into the issue queue. In this paper, we focus specifically on load cache misses and their dependent instructions. Simulations reveal that, for an 8-way processor, a 2K-entry WIB with a 32-entry issue queue can achieve speedups of 20%, 84%, and 50% over a conventional 32-entry issue queue for a subset of the SPEC CINT2000, SPEC CFP2000, and Olden benchmarks, respectively.
ISSN:1063-6897
2575-713X
DOI:10.1109/ISCA.2002.1003562