Efficient System-Level Design Space Exploration for High-level Synthesis using Pareto-Optimal Subspace Pruning

High-level synthesis (HLS) is a rapidly evolving and popular approach to designing, synthesizing, and optimizing embedded systems. Many HLS methodologies utilize design space exploration (DSE) at the post-synthesis stage to find Pareto-optimal hardware implementations for individual components. Howe...

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Bibliographic Details
Main Authors: Liao, Yuchao, Adegbija, Tosiron, Lysecky, Roman
Format: Conference Proceeding
Language:English
Subjects:
Asia
Design automation
Design methodology
design space exploration
embedded system
Embedded systems
Genetics
Hardware
high-level synthesis
Space exploration
subspace pruning
System-level optimization
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Summary:High-level synthesis (HLS) is a rapidly evolving and popular approach to designing, synthesizing, and optimizing embedded systems. Many HLS methodologies utilize design space exploration (DSE) at the post-synthesis stage to find Pareto-optimal hardware implementations for individual components. However, the design space for the system-level Pareto-optimal configurations is orders of magnitude larger than component-level design space, making existing approaches insufficient for system-level DSE. This paper presents Pruned Genetic Design Space Exploration (PG-DSE)-an approach to post-synthesis DSE that involves a pruning method to effectively reduce the system-level design space and an elitist genetic algorithm to accurately find the system-level Pareto-optimal configurations. We evaluate PG-DSE using an autonomous driving application subsystem (ADAS) and three synthetic systems with extremely large design spaces. Experimental results show that PGDSE can reduce the design space by several orders of magnitude compared to prior work while achieving higher quality results (an average improvement of 58.1x).
ISSN:2153-697X