Capacitance Engineering of GaN HEMT Technologies with Recessed Field Plate

This paper examines the effects of an improved source-connected field plate design used on multiple GaN HEMT gate length nodes. The modified field plate was shown to reduce the parasitic capacitances by suppressing the electric field in the drift region. As we reduced the device gate length to enabl...

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Bibliographic Details
Main Authors: Bothe, Kyle M., King, Matthew R., Guo, Jia, Liu, Yueying, Sriram, Saptha, Fisher, Jeremy, Sheppard, Scott T., Noori, Basim
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
field plate
gain
GaN HEMT
HEMTs
Integrated circuits
Logic gates
Performance evaluation
Power system measurements
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Summary:This paper examines the effects of an improved source-connected field plate design used on multiple GaN HEMT gate length nodes. The modified field plate was shown to reduce the parasitic capacitances by suppressing the electric field in the drift region. As we reduced the device gate length to enable higher frequency applications, we have demonstrated the difficulty to maintain Cgd at smaller nodes. With the modified structure, we achieved a reduced Cgd > 4 fF/mm and small signal gain > 2 dB by optimizing the recessed field plate on three gate length nodes. In turn, this produced power gain improvements of 0.7 dB to 1.4 dB while maintaining equivalent power densities. As the gate length node was scaled, the rate of Cgd improvement was less effective which cause a softening of the gain improvement. This trend has demonstrated the difficulties in controlling the parasitic capacitances for GaN HEMT designs as they scale to high frequency nodes.
ISSN:2831-4999
DOI:10.1109/BCICTS53451.2022.10051733