A Low Latency and Compact GCD Design using an Intelligent Seed-Selection Scheme of LL-PRNG

Stochastic computing has shown great promise for a variety of applications, including image processing circuits, due to its design simplicity and low power consumption. This work proposes a hardware efficient and low latency implementation of Greatest Common Divisor (GCD) circuit. It uses a Low Late...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2023-11, Vol.42 (11), p.1-1
Main Authors: Mitra, Shyamali, Goenka, Aadarsh G., Naskar, Mrinal K
Format: Article
Language:English
Subjects:
Blind Deconvolution
Circuit design
Clocks
Computer architecture
Correlation
Deconvolution
Generators
Greatest Common Divisor
Hardware
Image processing
LL-PRNG
Logic gates
Low Latency
Low latency communication
Power consumption
Random numbers
Stochastic Computing
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Summary:Stochastic computing has shown great promise for a variety of applications, including image processing circuits, due to its design simplicity and low power consumption. This work proposes a hardware efficient and low latency implementation of Greatest Common Divisor (GCD) circuit. It uses a Low Latency Parallel Random Number Generator (LL-PRNG) architecture with an intelligently chosen seed value that eliminates the use of correlators and decorrelators in the circuit, reducing the hardware overhead to a great extent. The proposed approach is compared with the conventional LFSR based design showing reasonable accuracy while the latency in computation greatly reduced. The circuit is evaluated for blind image deconvolution employing GCD and has shown encouraging results.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2023.3251746